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568 lines
11 KiB
PHP
568 lines
11 KiB
PHP
{
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This file is part of the Free Pascal run time library.
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Copyright (c) 2008 by the Free Pascal development team
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This file contains some helper routines for int64 and qword
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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{$ifndef CPUAVR_16_REGS}
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{$define FPC_SYSTEM_HAS_SHR_QWORD}
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// Simplistic version with checking if whole bytes can be shifted
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// Doesn't change bitshift portion even if possible because of byteshift
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// Shorter code but not shortest execution time version
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function fpc_shr_qword(value: qword; shift: ALUUInt): qword; assembler; nostackframe;
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[public, alias: 'FPC_SHR_QWORD']; compilerproc;
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label
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byteshift, bitshift, finish;
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asm
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// value passed in R25...R18
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// shift passed in R16
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// return value in R25...R18
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push R16
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andi R16, 63 // mask 64 bit relevant value per generic routine
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byteshift:
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breq finish // shift = 0, finished
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cpi R16, 8 // Check if shift is at least a byte
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brlo bitshift
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mov R18, R19 // if so, then shift all bytes right by 1 position
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mov R19, R20
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mov R20, R21
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mov R21, R22
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mov R22, R23
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mov R23, R24
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mov R24, R25
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clr R25 // and clear the high byte
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subi R16, 8 // subtract 8 bits from shift
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rjmp byteshift // check if another byte can be shifted
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bitshift: // shift all 8 bytes right by 1 bit
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lsr R25
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ror R24
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ror R23
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ror R22
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ror R21
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ror R20
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ror R19
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ror R18
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dec R16
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brne bitshift // until R16 = 0
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finish:
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pop R16
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end;
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function fpc_shr_qword(value: qword; shift: ALUUInt): qword; external name 'FPC_SHR_QWORD';
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{$define FPC_SYSTEM_HAS_SHL_QWORD}
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function fpc_shl_qword(value: qword; shift: ALUUInt): qword; assembler; nostackframe;
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[public, alias: 'FPC_SHL_QWORD']; compilerproc;
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label
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byteshift, bitshift, finish;
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asm
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// value passed in R25...R18
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// shift passed in R16
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// return value in R25...R18
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push R16
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andi R16, 63 // mask 64 bit relevant value per generic routine
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byteshift:
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breq finish // shift = 0, finished
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cpi R16, 8 // Check if shift is at least a byte
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brlo bitshift
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mov R25, R24 // if so, then shift all bytes left by 1 position
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mov R24, R23
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mov R23, R22
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mov R22, R21
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mov R21, R20
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mov R20, R19
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mov R19, R18
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clr R18 // and clear the high byte
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subi R16, 8 // subtract 8 bits from shift
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rjmp byteshift // check if another byte can be shifted
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bitshift: // shift all 8 bytes left by 1 bit
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lsl R18
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rol R19
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rol R20
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rol R21
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rol R22
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rol R23
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rol R24
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rol R25
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dec R16
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brne bitshift // until R16 = 0
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finish:
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pop R16
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end;
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function fpc_shl_qword(value: qword; shift: ALUUInt): qword; external name 'FPC_SHL_QWORD';
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{$define FPC_SYSTEM_HAS_SHL_INT64}
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function fpc_shl_int64(value: int64; shift: ALUUInt): int64;
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[public, alias: 'FPC_SHL_INT64']; compilerproc; inline;
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begin
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Result := fpc_shl_qword(qword(value), shift);
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end;
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{$define FPC_SYSTEM_HAS_SHR_INT64}
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// shr of signed int is same as shr of unsigned int (logical shift right)
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function fpc_shr_int64(value: int64; shift: ALUUInt): int64; [public, alias: 'FPC_SHR_INT64']; compilerproc;
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begin
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Result := fpc_shr_qword(qword(value), shift);
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end;
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{$define FPC_SYSTEM_HAS_DIV_QWORD}
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function fpc_div_qword(n,z : qword): qword; nostackframe; assembler; [public,alias: 'FPC_DIV_QWORD']; compilerproc;
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label
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start, div1, div2, div3, finish;
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asm
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// Symbol Name Register(s)
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// z (A) dividend R17, R16, R15, R14, R13, R12, R11, R10
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// n (B) divisor R25, R24, R23, R22, R21, R20, R19, R18
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// r (P) remainder R9, R8, R7, R6, R5, R4, R3, R2
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// i counter R26
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// 1 R27
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cp R25, R1
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cpc R24, R1
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cpc R23, R1
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cpc R22, R1
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cpc R21, R1
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cpc R20, R1
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cpc R19, R1
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cpc R18, R1
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brne .LNonZero
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{$ifdef CPUAVR_HAS_JMP_CALL}
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call fpc_divbyzero
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{$else CPUAVR_HAS_JMP_CALL}
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rcall fpc_divbyzero
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{$endif CPUAVR_HAS_JMP_CALL}
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.LNonZero:
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push R17
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push R16
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push R15
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push R14
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push R13
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push R12
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push R11
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push R10
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push R9
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push R8
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push R7
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push R6
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push R5
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push R4
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push R3
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push R2
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ldi R27, 1 // needed below for OR instruction
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start: // Start of division...
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clr R9 // clear remainder
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clr R8
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clr R7
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clr R6
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clr R5
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clr R4
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clr R3
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clr R2
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ldi R26, 64 // iterate over 64 bits
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div1:
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lsl R10 // shift left A_L
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rol R11
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rol R12
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rol R13
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rol R14
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rol R15
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rol R16
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rol R17
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rol R2 // shift left P with carry from A shift
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rol R3
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rol R4
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rol R5
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rol R6
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rol R7
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rol R8
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rol R9
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sub R2, R18 // Subtract B from P, P <= P - B
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sbc R3, R19
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sbc R4, R20
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sbc R5, R21
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sbc R6, R22
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sbc R7, R23
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sbc R8, R24
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sbc R9, R25
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brlo div2
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or R10, R27 // Set A[0] = 1
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rjmp div3
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div2: // negative branch, A[0] = 0 (default after shift), restore P
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add R2, R18 // restore old value of P
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adc R3, R19
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adc R4, R20
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adc R5, R21
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adc R6, R22
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adc R7, R23
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adc R8, R24
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adc R9, R25
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div3:
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dec R26
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breq finish
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rjmp div1
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finish:
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mov R25, R17 // Move answer from R17..10 to R25..18
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mov R24, R16
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mov R23, R15
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mov R22, R14
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mov R21, R13
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mov R20, R12
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mov R19, R11
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mov R18, R10
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pop R2
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pop R3
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pop R4
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pop R5
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pop R6
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pop R7
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pop R8
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pop R9
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pop R10
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pop R11
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pop R12
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pop R13
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pop R14
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pop R15
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pop R16
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pop R17
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end;
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function fpc_div_qword(n,z : qword): qword; external name 'FPC_DIV_QWORD';
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{$define FPC_SYSTEM_HAS_MOD_QWORD}
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function fpc_mod_qword(n,z : qword): qword; nostackframe; assembler; [public,alias: 'FPC_MOD_QWORD']; compilerproc;
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label
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start, div1, div2, div3, finish;
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asm
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// Symbol Name Register(s)
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// z (A) dividend R17, R16, R15, R14, R13, R12, R11, R10
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// n (B) divisor R25, R24, R23, R22, R21, R20, R19, R18
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// r (P) remainder R9, R8, R7, R6, R5, R4, R3, R2
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// i counter R26
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// 1 R27
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cp R25, R1
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cpc R24, R1
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cpc R23, R1
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cpc R22, R1
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cpc R21, R1
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cpc R20, R1
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cpc R19, R1
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cpc R18, R1
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brne .LNonZero
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{$ifdef CPUAVR_HAS_JMP_CALL}
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call fpc_divbyzero
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{$else CPUAVR_HAS_JMP_CALL}
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rcall fpc_divbyzero
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{$endif CPUAVR_HAS_JMP_CALL}
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.LNonZero:
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push R17
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push R16
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push R15
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push R14
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push R13
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push R12
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push R11
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push R10
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push R9
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push R8
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push R7
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push R6
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push R5
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push R4
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push R3
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push R2
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ldi R27, 1
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start: // Start of division...
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clr R9 // clear remainder
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clr R8
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clr R7
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clr R6
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clr R5
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clr R4
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clr R3
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clr R2
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ldi R26, 64 // iterate over 64 bits
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div1:
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lsl R10 // shift left A_L
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rol R11
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rol R12
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rol R13
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rol R14
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rol R15
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rol R16
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rol R17
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rol R2 // shift left P with carry from A shift
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rol R3
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rol R4
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rol R5
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rol R6
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rol R7
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rol R8
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rol R9
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sub R2, R18 // Subtract B from P, P <= P - B
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sbc R3, R19
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sbc R4, R20
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sbc R5, R21
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sbc R6, R22
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sbc R7, R23
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sbc R8, R24
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sbc R9, R25
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brlo div2
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or R10, R27 // Set A[0] = 1
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rjmp div3
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div2: // negative branch, A[0] = 0 (default after shift), restore P
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add R2, R18 // restore old value of P
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adc R3, R19
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adc R4, R20
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adc R5, R21
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adc R6, R22
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adc R7, R23
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adc R8, R24
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adc R9, R25
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div3:
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dec R26
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breq finish
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rjmp div1
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finish:
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mov R25, R9 // Move answer from R9..2 to R25..18
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mov R24, R8
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mov R23, R7
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mov R22, R6
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mov R21, R5
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mov R20, R4
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mov R19, R3
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mov R18, R2
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pop R2
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pop R3
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pop R4
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pop R5
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pop R6
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pop R7
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pop R8
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pop R9
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pop R10
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pop R11
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pop R12
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pop R13
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pop R14
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pop R15
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pop R16
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pop R17
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end;
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function fpc_mod_qword(n,z : qword): qword; external name 'FPC_MOD_QWORD';
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{$define FPC_SYSTEM_HAS_DIV_INT64}
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function fpc_div_int64(n,z : int64) : int64; nostackframe; assembler; [public,alias: 'FPC_DIV_INT64']; compilerproc;
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label
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pos1, pos2, fin;
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asm
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// Convert n, z to unsigned int, then call div_qword,
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// Restore sign if high bits of n xor z is negative
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// n divisor R25, R24, R23, R22, R21, R20, R19, R18
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// z dividend R17, R16, R15, R14, R13, R12, R11, R10
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// neg_result R30
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// one R31
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mov R30, R17 // store hi8(z)
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eor R30, R25 // hi8(z) XOR hi8(n), answer must be negative if MSB set
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// convert n to absolute
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ldi R31, 1 // 1 in R31 used later
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sub R25, r1 // subtract 0, just to check sign flag
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brpl pos1
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com R25
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com R24
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com R23
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com R22
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com R21
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com R20
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com R19
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com R18
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add R18, R31 // add 1
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adc R19, R1 // add carry bit
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adc R20, R1
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adc R21, R1
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adc R22, R1
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adc R23, R1
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adc R24, R1
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adc R25, R1
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pos1:
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sub R17, R1
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brpl pos2
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com R17
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com R16
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com R15
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com R14
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com R13
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com R12
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com R11
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com R10
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add R10, R31
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adc R11, R1
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adc R12, R1
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adc R13, R1
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adc R14, R1
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adc R15, R1
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adc R16, R1
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adc R17, R1
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pos2:
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{$ifdef CPUAVR_HAS_JMP_CALL}
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call fpc_div_qword
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{$else CPUAVR_HAS_JMP_CALL}
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rcall fpc_div_qword
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{$endif CPUAVR_HAS_JMP_CALL}
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sbrs R30, 7 // skip if bit 7 is cleared (result should be positive)
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rjmp fin
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com R25 // result from FPC_DIV_WORD in R25 ... R22
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com R24
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com R23
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com R22
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com R21
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com R20
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com R19
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com R18
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ldi R31, 1
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add R18, R31 // add 1
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adc R19, R1 // add carry bit
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adc R20, R1
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adc R21, R1
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adc R22, R1
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adc R23, R1
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adc R24, R1
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adc R25, R1
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fin:
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end;
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{$define FPC_SYSTEM_HAS_MOD_INT64}
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function fpc_mod_int64(n,z : int64) : int64; nostackframe; assembler; [public,alias: 'FPC_MOD_INT64']; compilerproc;
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label
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pos1, pos2, fin;
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asm
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// Convert n, z to unsigned int, then call mod_qword,
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// Restore sign if high bits of n xor z is negative
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// n divisor R25, R24, R23, R22, R21, R20, R19, R18
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// z dividend R17, R16, R15, R14, R13, R12, R11, R10
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// neg_result R30
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// one R31
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mov R30, R17 // store hi8(z)
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// convert n to absolute
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ldi R31, 1
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sub R25, r1 // subtract 0, just to check sign flag
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brpl pos1
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com R25
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com R24
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com R23
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com R22
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com R21
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com R20
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com R19
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com R18
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add R18, R31 // add 1
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adc R19, R1 // add carry bit
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adc R20, R1
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adc R21, R1
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adc R22, R1
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adc R23, R1
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adc R24, R1
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adc R25, R1
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pos1:
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sub R17, R1
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brpl pos2
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com R17
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com R16
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com R15
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com R14
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com R13
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com R12
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com R11
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com R10
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add R10, R31
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adc R11, R1
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adc R12, R1
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adc R13, R1
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adc R14, R1
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adc R15, R1
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adc R16, R1
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adc R17, R1
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pos2:
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{$ifdef CPUAVR_HAS_JMP_CALL}
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call fpc_mod_qword
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{$else CPUAVR_HAS_JMP_CALL}
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rcall fpc_mod_qword
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{$endif CPUAVR_HAS_JMP_CALL}
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sbrs R30, 7 // Not finished if sign bit is set
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rjmp fin
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com R25 // Convert to 2's complement
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com R24 // Complement all bits...
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com R23
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com R22
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com R21
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com R20
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com R19
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com R18
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ldi R31, 1
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add R18, R31 // ...and add 1 to answer
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adc R19, R1
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adc R20, R1
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adc R21, R1
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adc R22, R1
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adc R23, R1
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adc R24, R1
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adc R25, R1
|
|
fin:
|
|
end;
|
|
{$endif CPUAVR_16_REGS}
|