nickysn 94bcb9878a * reimplemented r28329 in a different way, as suggested by Jonas ... git-svn-id: trunk@28332 -		2014-08-07 19:36:52 +00:00
..
aoptcpu.pas	* optimize vmovaps/vmovapd after avx instructions	2014-05-01 19:20:35 +00:00
aoptcpub.pas
aoptcpud.pas
cgcpu.pas	+ cs_userbp optimizer switch, so on x86-64 the compiler can make use of rbp if it is not needed as frame pointer	2014-01-30 19:44:17 +00:00
cpubase.inc
cpuelf.pas
cpuinfo.pas	+ support for FMA intrinsic: if there is no hardware support, the compiler throws an error.	2014-04-13 19:21:54 +00:00
cpunode.pas	+ support overriding tdef/tsym methods with target-specific functionality:	2014-03-29 22:31:55 +00:00
cpupara.pas	* Win64 apparently expects records with single field of floating-point type to be passed the same way as that only field, i.e. in xmm register. Fixes tests/cg/tcalext6.pp.	2014-04-01 17:04:47 +00:00
cpupi.pas
cputarg.pas
hlcgcpu.pas
nx64add.pas
nx64cal.pas
nx64cnv.pas
nx64flw.pas	- Removed Win64 SEH code specific to results of managed types returned in registers. Since r26228 managed types are always returned in parameters.	2014-03-16 15:48:49 +00:00
nx64inl.pas
nx64mat.pas	* Moved x86_64 mod/div code to x86, with minimal changes to ensure it compiles on i386/i8086. Merging optimized division-by-const code from i386 is pending...	2014-06-11 01:42:46 +00:00
nx64set.pas
r8664ari.inc
r8664att.inc
r8664con.inc
r8664dwrf.inc
r8664int.inc
r8664iri.inc
r8664nasm.inc
r8664nor.inc
r8664num.inc
r8664ot.inc
r8664rni.inc
r8664sri.inc
r8664stab.inc
r8664std.inc
rax64att.pas
rax64int.pas
rgcpu.pas
symcpu.pas	* reimplemented r28329 in a different way, as suggested by Jonas	2014-08-07 19:36:52 +00:00
win64unw.pas
x8664ats.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664att.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664int.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664nop.inc	+ prove of concept how FMA4 could be supported in inline assembler	2014-03-20 21:25:38 +00:00
x8664op.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664pro.inc	* x86: Completely skip instructions that do not exist for target CPU bit width. The existing behavior of writing mnemonics and properties but no encoding allows an invalid instruction to be recognized by assembler reader or even generated by compiler, but it but won't assemble anyway.	2014-06-11 22:31:40 +00:00
x8664tab.inc	+ prove of concept how FMA4 could be supported in inline assembler	2014-03-20 21:25:38 +00:00