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7d459cf12a
alignment for each memory reference (mantis #12137, and test/packages/fcl-registry/tregistry1.pp on sparc). This also enables better code generation for packed records in many cases. o several changes were made to the compiler to minimise the chances of accidentally forgetting to set the alignment of memory references in the future: - reference_reset*() now has an extra alignment parameter - location_reset() can now only be used for non LOC_(C)REFERENCE, use location_reset_ref() for those (split the tloc enum so the compiler can catch errors using range checking) git-svn-id: trunk@12719 -
372 lines
12 KiB
ObjectPascal
372 lines
12 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
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development team
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This unit contains register renaming functionality
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit rropt386;
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{$i fpcdefs.inc}
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interface
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uses aasmbase,aasmtai,aasmdata,aasmcpu;
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procedure doRenaming(asml: TAsmList; first, last: tai);
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implementation
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uses
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{$ifdef replaceregdebug}cutils,{$endif}
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verbose,globals,cpubase,daopt386,csopt386,rgobj,
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cgbase,cgutils,cgobj;
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function canBeFirstSwitch(p: taicpu; supreg: tsuperregister): boolean;
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{ checks whether an operation on reg can be switched to another reg without an }
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{ additional mov, e.g. "addl $4,%reg1" can be changed to "leal 4(%reg1),%reg2" }
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begin
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canBeFirstSwitch := false;
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case p.opcode of
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A_MOV,A_MOVZX,A_MOVSX,A_LEA:
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canBeFirstSwitch :=
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(p.oper[1]^.typ = top_reg) and
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(getsupreg(p.oper[1]^.reg) = supreg);
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A_IMUL:
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canBeFirstSwitch :=
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(p.ops >= 2) and
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(p.oper[0]^.typ = top_const) and
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(getsupreg(p.oper[p.ops-1]^.reg) = supreg) and
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(not pTaiprop(p.optinfo)^.FlagsUsed);
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A_INC,A_DEC:
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canBeFirstSwitch :=
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(p.oper[0]^.typ = top_reg) and
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(p.opsize = S_L) and
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(not pTaiprop(p.optinfo)^.FlagsUsed);
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A_SUB,A_ADD:
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canBeFirstSwitch :=
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(p.oper[1]^.typ = top_reg) and
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(p.opsize = S_L) and
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(getsupreg(p.oper[1]^.reg) = supreg) and
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(p.oper[0]^.typ <> top_ref) and
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((p.opcode <> A_SUB) or
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(p.oper[0]^.typ = top_const)) and
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(not pTaiprop(p.optinfo)^.FlagsUsed);
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A_SHL:
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canBeFirstSwitch :=
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(p.opsize = S_L) and
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(p.oper[1]^.typ = top_reg) and
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(getsupreg(p.oper[1]^.reg) = supreg) and
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(p.oper[0]^.typ = top_const) and
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(p.oper[0]^.val in [1,2,3]) and
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(not pTaiprop(p.optinfo)^.FlagsUsed);
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end;
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end;
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procedure switchReg(var reg: tregister; reg1, reg2: tsuperregister);
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var
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supreg: tsuperregister;
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begin
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if (reg = NR_NO) or
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(getregtype(reg) <> R_INTREGISTER) then
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exit;
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supreg := getsupreg(reg);
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if (supreg = reg1) then
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setsupreg(reg,reg2)
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else if (supreg = reg2) then
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setsupreg(reg,reg1);
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end;
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procedure switchOp(var op: toper; reg1, reg2: tsuperregister);
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begin
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case op.typ of
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top_reg:
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switchReg(op.reg,reg1,reg2);
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top_ref:
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begin
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switchReg(op.ref^.base,reg1,reg2);
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switchReg(op.ref^.index,reg1,reg2);
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end;
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end;
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end;
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procedure doSwitchReg(hp: taicpu; reg1,reg2: tsuperregister);
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var
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opCount: longint;
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begin
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for opCount := 0 to hp.ops-1 do
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switchOp(hp.oper[opCount]^,reg1,reg2);
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end;
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procedure doFirstSwitch(p: taicpu; reg1, reg2: tsuperregister);
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var
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tmpRef: treference;
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begin
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case p.opcode of
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A_MOV,A_MOVZX,A_MOVSX,A_LEA:
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begin
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changeOp(p.oper[1]^,reg1,reg2);
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changeOp(p.oper[0]^,reg2,reg1);
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end;
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A_IMUL:
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begin
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p.ops := 3;
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p.loadreg(2,newreg(R_INTREGISTER,reg2,R_SUBWHOLE));
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changeOp(p.oper[1]^,reg2,reg1);
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end;
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A_INC,A_DEC:
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begin
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reference_reset(tmpref,1);
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tmpref.base := newreg(R_INTREGISTER,reg1,R_SUBWHOLE);
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case p.opcode of
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A_INC:
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tmpref.offset := 1;
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A_DEC:
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tmpref.offset := -1;
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end;
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p.ops := 2;
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p.opcode := A_LEA;
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p.loadreg(1,newreg(R_INTREGISTER,reg2,R_SUBWHOLE));
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p.loadref(0,tmpref);
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end;
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A_SUB,A_ADD:
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begin
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reference_reset(tmpref,1);
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tmpref.base := newreg(R_INTREGISTER,reg1,R_SUBWHOLE);
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case p.oper[0]^.typ of
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top_const:
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begin
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tmpref.offset := longint(p.oper[0]^.val);
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if p.opcode = A_SUB then
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tmpref.offset := - tmpRef.offset;
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end;
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top_ref:
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if (p.oper[0]^.ref^.refaddr=addr_full) then
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tmpref.symbol := p.oper[0]^.ref^.symbol
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else
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internalerror(200402263);
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top_reg:
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begin
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{ "addl %reg2,%reg1" must become "leal (%reg1,%reg1),%reg2" }
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{ since at this point reg1 holds the value that reg2 would }
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{ otherwise contain }
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tmpref.index := p.oper[0]^.reg;
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if (getsupreg(tmpref.index)=reg2) then
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setsupreg(tmpref.index,reg1);
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tmpref.scalefactor := 1;
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end;
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else internalerror(200010031);
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end;
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p.opcode := A_LEA;
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p.loadref(0,tmpref);
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p.loadreg(1,newreg(R_INTREGISTER,reg2,R_SUBWHOLE));
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end;
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A_SHL:
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begin
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reference_reset(tmpref,2);
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tmpref.index := newreg(R_INTREGISTER,reg1,R_SUBWHOLE);
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tmpref.scalefactor := 1 shl p.oper[0]^.val;
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p.opcode := A_LEA;
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p.loadref(0,tmpref);
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p.loadreg(1,newreg(R_INTREGISTER,reg2,R_SUBWHOLE));
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end;
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else internalerror(200010032);
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end;
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end;
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function switchRegs(asml: TAsmList; reg1, reg2: tsuperregister; start: tai): Boolean;
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{ change movl %reg1,%reg2 ... bla ... to ... bla with reg1 and reg2 switched }
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var
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endP, hp, lastreg1,lastreg2: tai;
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switchDone, switchLast, tmpResult, sequenceEnd, reg1Modified, reg2Modified: boolean;
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reg1StillUsed, reg2StillUsed, isInstruction: boolean;
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begin
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switchRegs := false;
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tmpResult := true;
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sequenceEnd := false;
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reg1Modified := false;
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reg2Modified := false;
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endP := start;
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while tmpResult and not sequenceEnd do
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begin
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tmpResult :=
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getNextInstruction(endP,endP);
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If tmpResult and
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not pTaiprop(endp.optinfo)^.canBeRemoved then
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begin
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{ if the newReg gets stored back to the oldReg, we can change }
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{ "mov %oldReg,%newReg; <operations on %newReg>; mov %newReg, }
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{ %oldReg" to "<operations on %oldReg>" }
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switchLast := storeBack(start,endP,reg1,reg2);
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reg1StillUsed := reg1 in pTaiprop(endp.optinfo)^.usedregs;
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reg2StillUsed := reg2 in pTaiprop(endp.optinfo)^.usedregs;
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isInstruction := endp.typ = ait_instruction;
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sequenceEnd :=
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switchLast or
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{ if both registers are released right before an instruction }
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{ that contains hardcoded regs, it's ok too }
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(not reg1StillUsed and not reg2StillUsed) or
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{ no support for (i)div, mul and imul with hardcoded operands }
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(((not isInstruction) or
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noHardCodedRegs(taicpu(endP),reg1,reg2)) and
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(not reg1StillUsed or
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(isInstruction and findRegDealloc(reg1,endP) and
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regLoadedWithNewValue(reg1,false,taicpu(endP)))) and
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(not reg2StillUsed or
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(isInstruction and findRegDealloc(reg2,endP) and
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regLoadedWithNewValue(reg2,false,taicpu(endP)))));
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{ we can't switch reg1 and reg2 in something like }
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{ movl %reg1,%reg2 }
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{ movl (%reg2),%reg2 }
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{ movl 4(%reg1),%reg1 }
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if reg2Modified and not(reg1Modified) and
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regReadByInstruction(reg1,endP) then
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begin
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tmpResult := false;
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break
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end;
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if not reg1Modified then
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begin
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reg1Modified := regModifiedByInstruction(reg1,endP);
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if reg1Modified and not canBeFirstSwitch(taicpu(endP),reg1) then
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begin
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tmpResult := false;
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break;
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end;
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end;
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if not reg2Modified then
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reg2Modified := regModifiedByInstruction(reg2,endP);
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tmpResult :=
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((not isInstruction) or
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(NoHardCodedRegs(taicpu(endP),reg1,reg2) and
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RegSizesOk(reg1,reg2,taicpu(endP))));
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if sequenceEnd then
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break;
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tmpResult :=
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tmpresult and
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(endp.typ <> ait_label) and
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((not isInstruction) or
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(not taicpu(endp).is_jmp));
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end;
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end;
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if tmpResult and sequenceEnd then
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begin
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switchRegs := true;
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reg1Modified := false;
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reg2Modified := false;
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lastreg1 := start;
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lastreg2 := start;
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getNextInstruction(start,hp);
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while hp <> endP do
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begin
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if (not pTaiprop(hp.optinfo)^.canberemoved) and
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(hp.typ = ait_instruction) then
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begin
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switchDone := false;
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if not reg1Modified then
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begin
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reg1Modified := regModifiedByInstruction(reg1,hp);
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if reg1Modified then
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begin
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doFirstSwitch(taicpu(hp),reg1,reg2);
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switchDone := true;
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end;
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end;
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if not switchDone then
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if reg1Modified then
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doSwitchReg(taicpu(hp),reg1,reg2)
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else
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doReplaceReg(taicpu(hp),reg2,reg1);
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end;
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if regininstruction(reg1,hp) then
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lastreg1 := hp;
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if regininstruction(reg2,hp) then
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lastreg2 := hp;
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getNextInstruction(hp,hp);
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end;
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if switchLast then
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begin
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lastreg1 := hp;
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lastreg2 := hp;
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{ this is in case of a storeback, make sure the same size of register }
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{ contents as the initial move is transfered }
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doSwitchReg(taicpu(hp),reg1,reg2);
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if taicpu(hp).opsize <> taicpu(start).opsize then
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begin
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taicpu(hp).opsize := taicpu(start).opsize;
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taicpu(hp).oper[0]^.reg := taicpu(start).oper[0]^.reg;
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taicpu(hp).oper[1]^.reg := taicpu(start).oper[1]^.reg;
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end;
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end
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else
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getLastInstruction(hp,hp);
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allocRegBetween(asmL,newreg(R_INTREGISTER,reg1,R_SUBWHOLE),start,lastreg1,
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ptaiprop(start.optinfo)^.usedregs);
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allocRegBetween(asmL,newreg(R_INTREGISTER,reg2,R_SUBWHOLE),start,lastreg2,
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ptaiprop(start.optinfo)^.usedregs);
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end;
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end;
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procedure doRenaming(asml: TAsmList; first, last: tai);
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var
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p: tai;
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begin
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p := First;
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SkipHead(p);
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while p <> last do
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begin
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case p.typ of
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ait_instruction:
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begin
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case taicpu(p).opcode of
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A_MOV:
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begin
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if not(pTaiprop(p.optinfo)^.canBeRemoved) and
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(taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).opsize = S_L) and
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(getsupreg(taicpu(p).oper[0]^.reg) in ([RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI])) and
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(getsupreg(taicpu(p).oper[1]^.reg) in ([RS_EAX,RS_EBX,RS_ECX,RS_EDX,RS_ESI,RS_EDI])) then
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if switchRegs(asml,getsupreg(taicpu(p).oper[0]^.reg),
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getsupreg(taicpu(p).oper[1]^.reg),p) then
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begin
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pTaiprop(p.optinfo)^.canBeRemoved := true;
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end;
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end;
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end;
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end;
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end;
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getNextInstruction(p,p);
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end;
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end;
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End.
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