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847 lines
29 KiB
ObjectPascal
847 lines
29 KiB
ObjectPascal
{
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Copyright (c) 1999-2008 by Mazen Neifer and Florian Klaempfl
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Contains the assembler object for the Z80
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit aasmcpu;
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{$i fpcdefs.inc}
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interface
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uses
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cclasses,
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globtype,globals,verbose,
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aasmbase,aasmtai,aasmdata,aasmsym,
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cgbase,cgutils,cpubase,cpuinfo,
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ogbase;
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const
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{ "mov reg,reg" source operand number }
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O_MOV_SOURCE = 1;
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{ "mov reg,reg" source operand number }
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O_MOV_DEST = 0;
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instabentries = {$i z80nop.inc}
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maxinfolen = 18;
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type
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{ Operand types }
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toperandtype=(
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OT_NONE,
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OT_IMM3, { 3-bit immediate value (bit number: [0..7]) }
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OT_IMM8, { 8-bit immediate value }
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OT_IMM16, { 16-bit immediate value }
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OT_IMM_VAL0, { the immediate value 0 }
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OT_IMM_VAL1, { the immediate value 1 }
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OT_IMM_VAL2, { the immediate value 2 }
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OT_IMM_RST, { immediate value in [$00,$08,$10,$18,$20,$28,$30,$38] }
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OT_IMM_PORT, { 8-bit immediate port number for the IN and OUT instructions }
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OT_REG8, { 8-bit register: A/B/C/D/E/H/L }
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OT_REG8_A, { register A }
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OT_REG8_I, { register I }
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OT_REG8_R, { register R }
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OT_REG8_C_PORT, { implied parameter of the IN and OUT instructions }
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OT_REG16_IX, { register IX }
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OT_REG16_IY, { register IY }
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OT_REG16_SP, { register SP }
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OT_REG16_BC_DE_HL_SP, { 16-bit register pair: BC/DE/HL/SP }
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OT_REG16_BC_DE_HL_AF, { 16-bit register pair: BC/DE/HL/AF }
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OT_REG16_BC_DE_IX_SP, { 16-bit register pair: BC/DE/IX/SP }
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OT_REG16_BC_DE_IY_SP, { 16-bit register pair: BC/DE/IY/SP }
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OT_REG16_DE, { 16-bit register pair DE }
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OT_REG16_HL, { 16-bit register pair HL }
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OT_REG16_AF, { 16-bit register pair AF }
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OT_REG16_AF_, { alternate register set, 16-bit register pair AF' }
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OT_RELJMP8, { 8-bit relative jump offset }
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OT_COND, { condition: NZ/Z/NC/C/PO/PE/P/M }
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OT_COND_C, { condition C }
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OT_COND_NC, { condition NC }
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OT_COND_Z, { condition Z }
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OT_COND_NZ, { condition NZ }
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OT_REF_ADDR16, { memory contents at address (nn = 16-bit immediate address) }
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OT_REF_BC, { memory contents at address in register BC }
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OT_REF_DE, { memory contents at address in register DE }
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OT_REF_HL, { memory contents at address in register HL }
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OT_REF_SP, { memory contents at address in register SP }
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OT_REF_IX, { memory contents at address in register IX }
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OT_REF_IY, { memory contents at address in register IY }
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OT_REF_IX_d, { memory contents at address in register IX+d, d is in [-128..127] }
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OT_REF_IY_d); { memory contents at address in register IY+d, d is in [-128..127] }
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timmoperandtype = OT_IMM3..OT_IMM_PORT;
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tregoperandtype = OT_REG8..OT_REG16_AF_;
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treg8operandtype = OT_REG8..OT_REG8_C_PORT;
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treg16operandtype = OT_REG16_IX..OT_REG16_AF_;
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tcondoperandtype = OT_COND..OT_COND_NZ;
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trefoperandtype = OT_REF_ADDR16..OT_REF_IY_d;
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trefoperandtypes = set of trefoperandtype;
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tinsentry = record
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opcode : tasmop;
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ops : byte;
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optypes : array[0..max_operands-1] of toperandtype;
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code : array[0..maxinfolen] of char;
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flags : longint;
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end;
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pinsentry=^tinsentry;
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{ taicpu }
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taicpu = class(tai_cpu_abstract_sym)
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private
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{ next fields are filled in pass1, so pass2 is faster }
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insentry : PInsEntry;
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inssize : shortint;
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function Matches(p:PInsEntry):boolean;
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function FindInsentry(objdata:TObjData):boolean;
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public
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constructor op_none(op : tasmop);
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constructor op_reg(op : tasmop;_op1 : tregister);
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constructor op_const(op : tasmop;_op1 : LongInt);
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constructor op_ref(op : tasmop;const _op1 : treference);
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constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
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constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
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constructor op_reg_const(op:tasmop; _op1: tregister; _op2: LongInt);
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constructor op_const_reg(op:tasmop; _op1: LongInt; _op2: tregister);
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constructor op_ref_reg(op : tasmop;const _op1 : treference;_op2 : tregister);
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constructor op_ref_const(op:tasmop; _op1: treference; _op2: LongInt);
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{ this is for Jmp instructions }
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constructor op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
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constructor op_sym(op : tasmop;_op1 : tasmsymbol);
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constructor op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
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procedure loadbool(opidx:longint;_b:boolean);
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{ register allocation }
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function is_same_reg_move(regtype: Tregistertype):boolean; override;
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{ register spilling code }
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function spilling_get_operation_type(opnr: longint): topertype;override;
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function GetString:string;
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end;
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tai_align = class(tai_align_abstract)
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{ nothing to add }
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end;
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procedure InitAsm;
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procedure DoneAsm;
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function spilling_create_load(const ref:treference;r:tregister):Taicpu;
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function spilling_create_store(r:tregister; const ref:treference):Taicpu;
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function is_ref_addr16(const ref:treference): Boolean;
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function is_ref_bc(const ref:treference): Boolean;
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function is_ref_de(const ref:treference): Boolean;
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function is_ref_hl(const ref:treference): Boolean;
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function is_ref_sp(const ref:treference): Boolean;
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function is_ref_ix(const ref:treference): Boolean;
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function is_ref_iy(const ref:treference): Boolean;
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function is_ref_ix_d(const ref:treference): Boolean;
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function is_ref_iy_d(const ref:treference): Boolean;
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function is_ref_opertype(const ref:treference;opertype:toperandtype): Boolean;
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function is_ref_in_opertypes(const ref:treference;const refopertypes:trefoperandtypes): Boolean;
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implementation
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{****************************************************************************
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Instruction table
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*****************************************************************************}
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type
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TInsTabCache=array[TasmOp] of longint;
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PInsTabCache=^TInsTabCache;
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const
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InsTab:array[0..instabentries-1] of TInsEntry={$i z80tab.inc}
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var
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InsTabCache : PInsTabCache;
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{*****************************************************************************
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taicpu Constructors
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*****************************************************************************}
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procedure taicpu.loadbool(opidx:longint;_b:boolean);
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begin
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if opidx>=ops then
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ops:=opidx+1;
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with oper[opidx]^ do
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begin
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if typ=top_ref then
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dispose(ref);
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b:=_b;
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typ:=top_bool;
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end;
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end;
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function taicpu.Matches(p: PInsEntry): boolean;
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function OperandsMatch(const oper: toper; const ot: toperandtype): boolean;
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begin
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case ot of
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OT_IMM3:
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result:=(oper.typ=top_const) and (oper.val>=0) and (oper.val<=7);
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OT_IMM8:
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{ todo: lo8, hi8 addresses }
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result:=(oper.typ=top_const) and (oper.val>=0) and (oper.val<=255);
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OT_IMM16:
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{ todo: addresses }
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result:=(oper.typ=top_const) and (oper.val>=0) and (oper.val<=65535);
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OT_IMM_VAL0:
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result:=(oper.typ=top_const) and (oper.val=0);
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OT_IMM_VAL1:
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result:=(oper.typ=top_const) and (oper.val=1);
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OT_IMM_VAL2:
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result:=(oper.typ=top_const) and (oper.val=2);
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OT_IMM_RST:
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result:=(oper.typ=top_const) and ((oper.val=$00) or (oper.val=$08) or
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(oper.val=$10) or (oper.val=$18) or
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(oper.val=$20) or (oper.val=$28) or
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(oper.val=$30) or (oper.val=$38));
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{todo: OT_IMM_PORT}
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OT_REG8:
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result:=(oper.typ=top_reg) and ((oper.reg=NR_A) or (oper.reg=NR_B) or
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(oper.reg=NR_C) or (oper.reg=NR_D) or
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(oper.reg=NR_E) or (oper.reg=NR_H) or
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(oper.reg=NR_L));
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OT_REG8_A:
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result:=(oper.typ=top_reg) and (oper.reg=NR_A);
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OT_REG8_I:
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result:=(oper.typ=top_reg) and (oper.reg=NR_I);
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OT_REG8_R:
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result:=(oper.typ=top_reg) and (oper.reg=NR_R);
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{todo: OT_REG8_C_PORT}
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OT_REG16_IX:
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result:=(oper.typ=top_reg) and (oper.reg=NR_IX);
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OT_REG16_IY:
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result:=(oper.typ=top_reg) and (oper.reg=NR_IY);
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OT_REG16_SP:
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result:=(oper.typ=top_reg) and (oper.reg=NR_SP);
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OT_REG16_BC_DE_HL_SP:
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result:=(oper.typ=top_reg) and ((oper.reg=NR_BC) or (oper.reg=NR_DE) or (oper.reg=NR_HL) or (oper.reg=NR_SP));
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OT_REG16_BC_DE_HL_AF:
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result:=(oper.typ=top_reg) and ((oper.reg=NR_BC) or (oper.reg=NR_DE) or (oper.reg=NR_HL) or (oper.reg=NR_AF));
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OT_REG16_BC_DE_IX_SP:
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result:=(oper.typ=top_reg) and ((oper.reg=NR_BC) or (oper.reg=NR_DE) or (oper.reg=NR_IX) or (oper.reg=NR_SP));
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OT_REG16_BC_DE_IY_SP:
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result:=(oper.typ=top_reg) and ((oper.reg=NR_BC) or (oper.reg=NR_DE) or (oper.reg=NR_IY) or (oper.reg=NR_SP));
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OT_REG16_DE:
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result:=(oper.typ=top_reg) and (oper.reg=NR_DE);
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OT_REG16_HL:
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result:=(oper.typ=top_reg) and (oper.reg=NR_HL);
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OT_REG16_AF:
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result:=(oper.typ=top_reg) and (oper.reg=NR_AF);
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OT_REG16_AF_:
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result:=(oper.typ=top_reg) and (oper.reg=NR_AF_);
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{todo: OT_RELJMP8}
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OT_REF_ADDR16,
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OT_REF_BC,
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OT_REF_DE,
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OT_REF_HL,
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OT_REF_SP,
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OT_REF_IX,
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OT_REF_IY,
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OT_REF_IX_d,
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OT_REF_IY_d:
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result:=(oper.typ=top_ref) and is_ref_opertype(oper.ref^,ot);
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else
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internalerror(2020042901);
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end;
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end;
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var
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i: Integer;
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begin
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result:=false;
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{ Check the opcode }
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if p^.opcode<>opcode then
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exit;
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{ The opcode doesn't support conditions, but we have a condition?
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That's an invalid instruction, don't match it against anything. }
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if (condition<>C_NONE) and not (opcode in cond_instructions) then
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exit;
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{ if our opcode supports a condition, but our operation doesn't have
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one, and we're matching it with an instruction entry 'p' that has a
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condition, then it doesn't match }
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if (opcode in cond_instructions) and (condition=C_None) and
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(p^.ops>0) and (p^.optypes[0] in [OT_COND..OT_COND_NZ]) then
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exit;
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{ instruction has a condition? }
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if (opcode in cond_instructions) and (condition<>C_None) then
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begin
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{ Check the operand count }
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if p^.ops<>(ops+1) then
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exit;
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{ Check the condition }
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case p^.optypes[0] of
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OT_COND:
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{ any condition accepted };
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OT_COND_C:
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if condition<>C_C then
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exit;
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OT_COND_NC:
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if condition<>C_NC then
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exit;
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OT_COND_Z:
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if condition<>C_Z then
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exit;
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OT_COND_NZ:
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if condition<>C_NZ then
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exit;
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else
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{ no condition in 'p'? Then it's not a match! }
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exit;
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end;
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{ Check the operands }
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for i:=1 to p^.ops-1 do
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if not OperandsMatch(oper[i-1]^,p^.optypes[i]) then
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exit;
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end
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else
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{ no condition }
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begin
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{ Check the operand count }
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if p^.ops<>ops then
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exit;
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{ Check the operands }
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for i:=0 to p^.ops-1 do
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if not OperandsMatch(oper[i]^,p^.optypes[i]) then
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exit;
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end;
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result:=true;
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end;
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function taicpu.FindInsentry(objdata: TObjData): boolean;
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var
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i : longint;
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begin
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result:=false;
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{ Things which may only be done once, not when a second pass is done to
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optimize }
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if (Insentry=nil) {or (IF_PASS2 in InsEntry^.flags)} then
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begin
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{ set the file postion }
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current_filepos:=fileinfo;
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end
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else
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begin
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{ we've already an insentry so it's valid }
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result:=true;
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exit;
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end;
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{ Lookup opcode in the table }
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InsSize:=-1;
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i:=instabcache^[opcode];
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if i=-1 then
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begin
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Message1(asmw_e_opcode_not_in_table,std_op2str[opcode]);
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exit;
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end;
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insentry:=@instab[i];
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while (insentry^.opcode=opcode) do
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begin
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if matches(insentry) then
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begin
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result:=true;
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exit;
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end;
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inc(insentry);
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end;
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Message1(asmw_e_invalid_opcode_and_operands,GetString);
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{ No instruction found, set insentry to nil and inssize to -1 }
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insentry:=nil;
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inssize:=-1;
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end;
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constructor taicpu.op_none(op : tasmop);
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begin
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inherited create(op);
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end;
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constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
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begin
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inherited create(op);
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ops:=1;
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loadreg(0,_op1);
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end;
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constructor taicpu.op_ref(op : tasmop;const _op1 : treference);
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begin
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inherited create(op);
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ops:=1;
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loadref(0,_op1);
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end;
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constructor taicpu.op_const(op : tasmop;_op1 : LongInt);
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begin
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inherited create(op);
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ops:=1;
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loadconst(0,_op1);
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end;
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constructor taicpu.op_reg_reg(op : tasmop;_op1,_op2 : tregister);
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begin
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inherited create(op);
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ops:=2;
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loadreg(0,_op1);
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loadreg(1,_op2);
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end;
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constructor taicpu.op_reg_const(op:tasmop; _op1: tregister; _op2: LongInt);
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begin
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inherited create(op);
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ops:=2;
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loadreg(0,_op1);
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loadconst(1,_op2);
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end;
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constructor taicpu.op_const_reg(op:tasmop; _op1: LongInt; _op2: tregister);
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begin
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inherited create(op);
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ops:=2;
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loadconst(0,_op1);
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loadreg(1,_op2);
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end;
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constructor taicpu.op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
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begin
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inherited create(op);
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ops:=2;
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loadreg(0,_op1);
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loadref(1,_op2);
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end;
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constructor taicpu.op_ref_reg(op : tasmop;const _op1 : treference;_op2 : tregister);
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begin
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inherited create(op);
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ops:=2;
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loadref(0,_op1);
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loadreg(1,_op2);
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end;
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constructor taicpu.op_ref_const(op: tasmop; _op1: treference; _op2: LongInt);
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begin
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inherited create(op);
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ops:=2;
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loadref(0,_op1);
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loadconst(1,_op2);
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end;
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constructor taicpu.op_cond_sym(op : tasmop;cond:TAsmCond;_op1 : tasmsymbol);
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begin
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inherited create(op);
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is_jmp:=op in jmp_instructions;
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condition:=cond;
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ops:=1;
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loadsymbol(0,_op1,0);
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end;
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constructor taicpu.op_sym(op : tasmop;_op1 : tasmsymbol);
|
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begin
|
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inherited create(op);
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is_jmp:=op in jmp_instructions;
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ops:=1;
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loadsymbol(0,_op1,0);
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end;
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|
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constructor taicpu.op_sym_ofs(op : tasmop;_op1 : tasmsymbol;_op1ofs:longint);
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begin
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inherited create(op);
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ops:=1;
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loadsymbol(0,_op1,_op1ofs);
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end;
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function taicpu.is_same_reg_move(regtype: Tregistertype):boolean;
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begin
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result:=(
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((opcode in [A_LD]) and (regtype = R_INTREGISTER))
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) and
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(ops=2) and
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(oper[0]^.typ=top_reg) and
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(oper[1]^.typ=top_reg) and
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(oper[0]^.reg=oper[1]^.reg);
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end;
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function taicpu.spilling_get_operation_type(opnr: longint): topertype;
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begin
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result:=operand_read;
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case opcode of
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A_LD,
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A_POP:
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if opnr=0 then
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result:=operand_write;
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A_PUSH,
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A_BIT,
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A_CP,
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A_DJNZ,
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A_JR,
|
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A_JP,
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A_CALL,
|
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A_RET,
|
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A_RETI,
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A_RETN,
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A_RST,
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A_IM:
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;
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A_SET,
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A_RES:
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if opnr=1 then
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result:=operand_readwrite;
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A_EX:
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result:=operand_readwrite;
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else
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begin
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if opnr=0 then
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result:=operand_readwrite;
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end;
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end;
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end;
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|
|
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function taicpu.GetString: string;
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var
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//i : longint;
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s : string;
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//regnr: string;
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//addsize : boolean;
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begin
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s:='['+std_op2str[opcode];
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//for i:=0 to ops-1 do
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// begin
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// with oper[i]^ do
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// begin
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// if i=0 then
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// s:=s+' '
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// else
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// s:=s+',';
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// { type }
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// addsize:=false;
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//
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// regnr := '';
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// if getregtype(reg) = R_MMREGISTER then
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// str(getsupreg(reg),regnr);
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//
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// if (ot and OT_XMMREG)=OT_XMMREG then
|
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// s:=s+'xmmreg' + regnr
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// else
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// if (ot and OT_YMMREG)=OT_YMMREG then
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// s:=s+'ymmreg' + regnr
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// else
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// if (ot and OT_ZMMREG)=OT_ZMMREG then
|
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// s:=s+'zmmreg' + regnr
|
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//
|
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// else
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// if (ot and OT_REG_EXTRA_MASK)=OT_MMXREG then
|
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// s:=s+'mmxreg'
|
|
// else
|
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// if (ot and OT_REG_EXTRA_MASK)=OT_FPUREG then
|
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// s:=s+'fpureg'
|
|
// else
|
|
// if (ot and OT_REGISTER)=OT_REGISTER then
|
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// begin
|
|
// s:=s+'reg';
|
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// addsize:=true;
|
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// end
|
|
// else
|
|
// if (ot and OT_IMMEDIATE)=OT_IMMEDIATE then
|
|
// begin
|
|
// s:=s+'imm';
|
|
// addsize:=true;
|
|
// end
|
|
// else
|
|
// if (ot and OT_MEMORY)=OT_MEMORY then
|
|
// begin
|
|
// s:=s+'mem';
|
|
// addsize:=true;
|
|
// end
|
|
// else
|
|
// s:=s+'???';
|
|
// { size }
|
|
// if addsize then
|
|
// begin
|
|
// if (ot and OT_BITS8)<>0 then
|
|
// s:=s+'8'
|
|
// else
|
|
// if (ot and OT_BITS16)<>0 then
|
|
// s:=s+'16'
|
|
// else
|
|
// if (ot and OT_BITS32)<>0 then
|
|
// s:=s+'32'
|
|
// else
|
|
// if (ot and OT_BITS64)<>0 then
|
|
// s:=s+'64'
|
|
// else
|
|
// if (ot and OT_BITS128)<>0 then
|
|
// s:=s+'128'
|
|
// else
|
|
// if (ot and OT_BITS256)<>0 then
|
|
// s:=s+'256'
|
|
// else
|
|
// if (ot and OT_BITS512)<>0 then
|
|
// s:=s+'512'
|
|
// else
|
|
// s:=s+'??';
|
|
// { signed }
|
|
// if (ot and OT_SIGNED)<>0 then
|
|
// s:=s+'s';
|
|
// end;
|
|
//
|
|
// if vopext <> 0 then
|
|
// begin
|
|
// str(vopext and $07, regnr);
|
|
// if vopext and OTVE_VECTOR_WRITEMASK = OTVE_VECTOR_WRITEMASK then
|
|
// s := s + ' {k' + regnr + '}';
|
|
//
|
|
// if vopext and OTVE_VECTOR_ZERO = OTVE_VECTOR_ZERO then
|
|
// s := s + ' {z}';
|
|
//
|
|
// if vopext and OTVE_VECTOR_SAE = OTVE_VECTOR_SAE then
|
|
// s := s + ' {sae}';
|
|
//
|
|
//
|
|
// if vopext and OTVE_VECTOR_BCST = OTVE_VECTOR_BCST then
|
|
// case vopext and OTVE_VECTOR_BCST_MASK of
|
|
// OTVE_VECTOR_BCST2: s := s + ' {1to2}';
|
|
// OTVE_VECTOR_BCST4: s := s + ' {1to4}';
|
|
// OTVE_VECTOR_BCST8: s := s + ' {1to8}';
|
|
// OTVE_VECTOR_BCST16: s := s + ' {1to16}';
|
|
// end;
|
|
//
|
|
// if vopext and OTVE_VECTOR_ER = OTVE_VECTOR_ER then
|
|
// case vopext and OTVE_VECTOR_ER_MASK of
|
|
// OTVE_VECTOR_RNSAE: s := s + ' {rn-sae}';
|
|
// OTVE_VECTOR_RDSAE: s := s + ' {rd-sae}';
|
|
// OTVE_VECTOR_RUSAE: s := s + ' {ru-sae}';
|
|
// OTVE_VECTOR_RZSAE: s := s + ' {rz-sae}';
|
|
// end;
|
|
//
|
|
// end;
|
|
// end;
|
|
// end;
|
|
GetString:=s+']';
|
|
end;
|
|
|
|
|
|
function spilling_create_load(const ref:treference;r:tregister):Taicpu;
|
|
begin
|
|
case getregtype(r) of
|
|
R_INTREGISTER :
|
|
result:=taicpu.op_reg_ref(A_LD,r,ref)
|
|
else
|
|
internalerror(200401041);
|
|
end;
|
|
end;
|
|
|
|
|
|
function spilling_create_store(r:tregister; const ref:treference):Taicpu;
|
|
begin
|
|
case getregtype(r) of
|
|
R_INTREGISTER :
|
|
result:=taicpu.op_ref_reg(A_LD,ref,r);
|
|
else
|
|
internalerror(200401041);
|
|
end;
|
|
end;
|
|
|
|
|
|
function is_ref_addr16(const ref: treference): Boolean;
|
|
begin
|
|
result:=(ref.base=NR_NO) and (ref.index=NR_NO);
|
|
end;
|
|
|
|
|
|
function is_ref_bc(const ref: treference): Boolean;
|
|
begin
|
|
result:=(((ref.base=NR_BC) and (ref.index=NR_NO)) or
|
|
((ref.base=NR_NO) and (ref.index=NR_BC))) and
|
|
(ref.offset=0) and (ref.scalefactor<=1) and
|
|
(ref.symbol=nil) and (ref.relsymbol=nil);
|
|
end;
|
|
|
|
|
|
function is_ref_de(const ref: treference): Boolean;
|
|
begin
|
|
result:=(((ref.base=NR_DE) and (ref.index=NR_NO)) or
|
|
((ref.base=NR_NO) and (ref.index=NR_DE))) and
|
|
(ref.offset=0) and (ref.scalefactor<=1) and
|
|
(ref.symbol=nil) and (ref.relsymbol=nil);
|
|
end;
|
|
|
|
|
|
function is_ref_hl(const ref: treference): Boolean;
|
|
begin
|
|
result:=(((ref.base=NR_HL) and (ref.index=NR_NO)) or
|
|
((ref.base=NR_NO) and (ref.index=NR_HL))) and
|
|
(ref.offset=0) and (ref.scalefactor<=1) and
|
|
(ref.symbol=nil) and (ref.relsymbol=nil);
|
|
end;
|
|
|
|
|
|
function is_ref_sp(const ref: treference): Boolean;
|
|
begin
|
|
result:=(((ref.base=NR_SP) and (ref.index=NR_NO)) or
|
|
((ref.base=NR_NO) and (ref.index=NR_SP))) and
|
|
(ref.offset=0) and (ref.scalefactor<=1) and
|
|
(ref.symbol=nil) and (ref.relsymbol=nil);
|
|
end;
|
|
|
|
|
|
function is_ref_ix(const ref: treference): Boolean;
|
|
begin
|
|
result:=(((ref.base=NR_IX) and (ref.index=NR_NO)) or
|
|
((ref.base=NR_NO) and (ref.index=NR_IX))) and
|
|
(ref.offset=0) and (ref.scalefactor<=1) and
|
|
(ref.symbol=nil) and (ref.relsymbol=nil);
|
|
end;
|
|
|
|
|
|
function is_ref_iy(const ref: treference): Boolean;
|
|
begin
|
|
result:=(((ref.base=NR_IY) and (ref.index=NR_NO)) or
|
|
((ref.base=NR_NO) and (ref.index=NR_IY))) and
|
|
(ref.offset=0) and (ref.scalefactor<=1) and
|
|
(ref.symbol=nil) and (ref.relsymbol=nil);
|
|
end;
|
|
|
|
|
|
function is_ref_ix_d(const ref: treference): Boolean;
|
|
begin
|
|
result:=(((ref.base=NR_IX) and (ref.index=NR_NO)) or
|
|
((ref.base=NR_NO) and (ref.index=NR_IX))) and
|
|
(ref.offset>=-128) and (ref.offset<=127) and (ref.scalefactor<=1) and
|
|
(ref.symbol=nil) and (ref.relsymbol=nil);
|
|
end;
|
|
|
|
|
|
function is_ref_iy_d(const ref: treference): Boolean;
|
|
begin
|
|
result:=(((ref.base=NR_IY) and (ref.index=NR_NO)) or
|
|
((ref.base=NR_NO) and (ref.index=NR_IY))) and
|
|
(ref.offset>=-128) and (ref.offset<=127) and (ref.scalefactor<=1) and
|
|
(ref.symbol=nil) and (ref.relsymbol=nil);
|
|
end;
|
|
|
|
|
|
function is_ref_opertype(const ref: treference; opertype: toperandtype): Boolean;
|
|
begin
|
|
case opertype of
|
|
OT_REF_ADDR16:
|
|
result:=is_ref_addr16(ref);
|
|
OT_REF_BC:
|
|
result:=is_ref_bc(ref);
|
|
OT_REF_DE:
|
|
result:=is_ref_de(ref);
|
|
OT_REF_HL:
|
|
result:=is_ref_hl(ref);
|
|
OT_REF_SP:
|
|
result:=is_ref_sp(ref);
|
|
OT_REF_IX:
|
|
result:=is_ref_ix(ref);
|
|
OT_REF_IY:
|
|
result:=is_ref_iy(ref);
|
|
OT_REF_IX_d:
|
|
result:=is_ref_ix_d(ref);
|
|
OT_REF_IY_d:
|
|
result:=is_ref_iy_d(ref);
|
|
else
|
|
internalerror(2020041801);
|
|
end;
|
|
end;
|
|
|
|
|
|
function is_ref_in_opertypes(const ref: treference; const refopertypes: trefoperandtypes): Boolean;
|
|
var
|
|
ot: trefoperandtype;
|
|
begin
|
|
result:=true;
|
|
for ot:=low(trefoperandtypes) to high(trefoperandtypes) do
|
|
if (ot in refopertypes) and is_ref_opertype(ref,ot) then
|
|
exit;
|
|
result:=false;
|
|
end;
|
|
|
|
|
|
{****************************************************************************
|
|
Instruction table
|
|
*****************************************************************************}
|
|
|
|
procedure BuildInsTabCache;
|
|
var
|
|
i : longint;
|
|
begin
|
|
new(instabcache);
|
|
FillChar(instabcache^,sizeof(tinstabcache),$ff);
|
|
i:=0;
|
|
while (i<InsTabEntries) do
|
|
begin
|
|
if InsTabCache^[InsTab[i].OPcode]=-1 then
|
|
InsTabCache^[InsTab[i].OPcode]:=i;
|
|
inc(i);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure InitAsm;
|
|
begin
|
|
if not assigned(instabcache) then
|
|
BuildInsTabCache;
|
|
end;
|
|
|
|
|
|
procedure DoneAsm;
|
|
begin
|
|
if assigned(instabcache) then
|
|
begin
|
|
dispose(instabcache);
|
|
instabcache:=nil;
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
cai_cpu:=taicpu;
|
|
cai_align:=tai_align;
|
|
end.
|