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ddba821561
from cpubase unit to a method in the tcg class. The reason for doing that is that this is now a standard part of the 16-bit and 8-bit code generators and moving to the tcg class allows doing extra checks (not done yet, but for example, in the future, we can keep track of whether there was an extra register allocated with getintregister and halt with an internalerror in case GetNextReg() is called for registers, which weren't allocated as a part of a sequence, therefore catching a certain class of 8-bit and 16-bit code generator bugs at compile time, instead of generating wrong code). - removed GetLastReg() from avr's cpubase unit, because it isn't used for anything. It might be added to the tcg class, in case it's ever needed, but for now I've left it out. * GetOffsetReg() and GetOffsetReg64() were also moved to the tcg unit. git-svn-id: trunk@37180 -
303 lines
10 KiB
ObjectPascal
303 lines
10 KiB
ObjectPascal
{
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Copyright (c) 2008 by Florian Klaempfl
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Code generation for add nodes on the AVR
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit navradd;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncgadd,cpubase;
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type
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TAVRAddNode = class(tcgaddnode)
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private
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function GetResFlags(unsigned:Boolean):TResFlags;
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protected
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function pass_1 : tnode;override;
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procedure second_cmpordinal;override;
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procedure second_cmpsmallset;override;
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procedure second_cmp64bit;override;
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procedure second_cmp;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,paramgr,
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aasmbase,aasmtai,aasmdata,aasmcpu,defutil,htypechk,
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cgbase,cgutils,cgcpu,
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cpuinfo,pass_1,pass_2,procinfo,
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cpupara,
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ncon,nset,nadd,
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ncgutil,tgobj,rgobj,rgcpu,cgobj,cg64f32,
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hlcgobj;
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{*****************************************************************************
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TAVRAddNode
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*****************************************************************************}
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function tavraddnode.GetResFlags(unsigned:Boolean):TResFlags;
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begin
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case NodeType of
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equaln:
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GetResFlags:=F_EQ;
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unequaln:
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GetResFlags:=F_NE;
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else
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if not(unsigned) then
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begin
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if nf_swapped in flags then
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case NodeType of
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ltn:
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GetResFlags:=F_NotPossible;
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lten:
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GetResFlags:=F_GE;
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gtn:
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GetResFlags:=F_LT;
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gten:
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GetResFlags:=F_NotPossible;
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else
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internalerror(2014082020);
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_LT;
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lten:
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GetResFlags:=F_NotPossible;
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gtn:
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GetResFlags:=F_NotPossible;
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gten:
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GetResFlags:=F_GE;
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else
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internalerror(2014082021);
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end;
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end
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else
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begin
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if nf_swapped in Flags then
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case NodeType of
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ltn:
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GetResFlags:=F_NotPossible;
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lten:
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GetResFlags:=F_SH;
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gtn:
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GetResFlags:=F_LO;
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gten:
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GetResFlags:=F_NotPossible;
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else
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internalerror(2014082022);
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_LO;
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lten:
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GetResFlags:=F_NotPossible;
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gtn:
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GetResFlags:=F_NotPossible;
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gten:
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GetResFlags:=F_SH;
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else
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internalerror(2014082023);
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end;
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end;
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end;
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end;
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procedure tavraddnode.second_cmpsmallset;
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procedure gencmp(tmpreg1,tmpreg2 : tregister);
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var
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i : byte;
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CP,tmpreg1,tmpreg2));
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for i:=2 to tcgsize2size[left.location.size] do
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begin
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tmpreg1:=cg.GetNextReg(tmpreg1);
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tmpreg2:=cg.GetNextReg(tmpreg2);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,tmpreg1,tmpreg2));
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end;
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end;
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var
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tmpreg : tregister;
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begin
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pass_left_right;
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location_reset(location,LOC_FLAGS,OS_NO);
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force_reg_left_right(false,false);
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case nodetype of
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equaln:
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begin
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gencmp(left.location.register,right.location.register);
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location.resflags:=F_EQ;
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end;
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unequaln:
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begin
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gencmp(left.location.register,right.location.register);
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location.resflags:=F_NE;
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end;
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lten,
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gten:
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begin
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if (not(nf_swapped in flags) and
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(nodetype = lten)) or
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((nf_swapped in flags) and
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(nodetype = gten)) then
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swapleftright;
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_AND,location.size,
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left.location.register,right.location.register,tmpreg);
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gencmp(tmpreg,right.location.register);
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location.resflags:=F_EQ;
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end;
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else
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internalerror(2004012401);
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end;
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end;
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procedure tavraddnode.second_cmp;
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var
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unsigned : boolean;
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tmpreg1,tmpreg2 : tregister;
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i : longint;
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begin
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pass_left_right;
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force_reg_left_right(true,true);
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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if getresflags(unsigned)=F_NotPossible then
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begin
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swapleftright;
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{ if we have to swap back and left is a constant, force it to a register because we cannot generate
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the needed code using a constant }
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if (left.location.loc=LOC_CONSTANT) and (left.location.value<>0) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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end;
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if right.location.loc=LOC_CONSTANT then
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begin
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{ decrease register pressure on registers >= r16 }
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if (right.location.value and $ff)=0 then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CP,left.location.register,NR_R1))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CPI,left.location.register,right.location.value and $ff))
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end
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{ on the left side, we allow only a constant if it is 0 }
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else if (left.location.loc=LOC_CONSTANT) and (left.location.value=0) then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CP,NR_R1,right.location.register))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CP,left.location.register,right.location.register));
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tmpreg1:=left.location.register;
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tmpreg2:=right.location.register;
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for i:=2 to tcgsize2size[left.location.size] do
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begin
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if i=5 then
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begin
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if left.location.loc<>LOC_CONSTANT then
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tmpreg1:=left.location.registerhi;
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if right.location.loc<>LOC_CONSTANT then
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tmpreg2:=right.location.registerhi;
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end
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else
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begin
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if left.location.loc<>LOC_CONSTANT then
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tmpreg1:=cg.GetNextReg(tmpreg1);
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if right.location.loc<>LOC_CONSTANT then
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tmpreg2:=cg.GetNextReg(tmpreg2);
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end;
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if right.location.loc=LOC_CONSTANT then
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begin
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{ just use R1? }
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if ((right.location.value64 shr ((i-1)*8)) and $ff)=0 then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,tmpreg1,NR_R1))
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else
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begin
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tmpreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_8);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_8,(right.location.value64 shr ((i-1)*8)) and $ff,tmpreg2);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,tmpreg1,tmpreg2));
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end;
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end
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{ above it is checked, if left=0, then a constant is allowed }
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else if (left.location.loc=LOC_CONSTANT) and (left.location.value=0) then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,NR_R1,tmpreg2))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_CPC,tmpreg1,tmpreg2));
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end;
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned);
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end;
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procedure tavraddnode.second_cmp64bit;
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begin
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second_cmp;
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end;
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function tavraddnode.pass_1 : tnode;
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begin
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result:=inherited pass_1;
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{$ifdef dummy}
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if not(assigned(result)) then
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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if is_64bit(left.resultdef) and
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((nodetype in [equaln,unequaln]) or
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(unsigned and (nodetype in [ltn,lten,gtn,gten]))
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) then
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expectloc:=LOC_FLAGS;
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end;
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{ handling boolean expressions }
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if not(assigned(result)) and
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(
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not(is_boolean(left.resultdef)) or
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not(is_boolean(right.resultdef)) or
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is_dynamic_array(left.resultdef)
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) then
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expectloc:=LOC_FLAGS;
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{$endif dummy}
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end;
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procedure tavraddnode.second_cmpordinal;
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begin
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second_cmp;
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end;
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begin
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caddnode:=tavraddnode;
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end.
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