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https://gitlab.com/freepascal.org/fpc/source.git
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b7fe6797bf
http://svn.freepascal.org/svn/fpc/branches/linker/compiler ........ r2921 | peter | 2006-03-15 08:35:00 +0100 (Wed, 15 Mar 2006) | 2 lines * pass ObjectWriter to ObjectOuput ........ r2922 | peter | 2006-03-15 12:40:30 +0100 (Wed, 15 Mar 2006) | 2 lines * refactor asmdata ........ r2925 | peter | 2006-03-15 16:09:39 +0100 (Wed, 15 Mar 2006) | 3 lines * add cfi to asmdata * move asmlist, asmcfi, asmdata to own unit ........ git-svn-id: trunk@2932 -
723 lines
31 KiB
ObjectPascal
723 lines
31 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate PowerPC assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nppcmat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat;
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type
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tppcmoddivnode = class(tmoddivnode)
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function pass_1: tnode;override;
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procedure pass_2;override;
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end;
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tppcshlshrnode = class(tshlshrnode)
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procedure pass_2;override;
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{ everything will be handled in pass_2 }
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function first_shlshr64bitint: tnode; override;
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end;
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tppcunaryminusnode = class(tunaryminusnode)
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procedure pass_2;override;
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end;
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tppcnotnode = class(tnotnode)
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procedure pass_2;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,
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aasmbase,aasmcpu,aasmtai,aasmdata,
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defutil,
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cgbase,cgutils,cgobj,pass_2,
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ncon,procinfo,
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cpubase,
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ncgutil,cgcpu;
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{$ifopt r+}
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{$r-}
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{$define rangeon}
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{$endif}
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{$ifopt q+}
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{$r-}
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{$define overflowon}
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{$endif}
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{ helper functions }
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procedure getmagic_unsigned32(d : dword; out magic_m : dword; out magic_add : boolean; out magic_shift : dword);
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var
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p : longint;
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nc, delta, q1, r1, q2, r2 : dword;
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begin
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assert(d > 0);
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magic_add := false;
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nc := - 1 - (-d) mod d;
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p := 31; { initialize p }
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q1 := $80000000 div nc; { initialize q1 = 2p/nc }
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r1 := $80000000 - q1*nc; { initialize r1 = rem(2p,nc) }
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q2 := $7FFFFFFF div d; { initialize q2 = (2p-1)/d }
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r2 := $7FFFFFFF - q2*d; { initialize r2 = rem((2p-1),d) }
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repeat
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inc(p);
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if (r1 >= (nc - r1)) then begin
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q1 := 2 * q1 + 1; { update q1 }
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r1 := 2*r1 - nc; { update r1 }
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end else begin
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q1 := 2*q1; { update q1 }
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r1 := 2*r1; { update r1 }
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end;
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if ((r2 + 1) >= (d - r2)) then begin
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if (q2 >= $7FFFFFFF) then
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magic_add := true;
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q2 := 2*q2 + 1; { update q2 }
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r2 := 2*r2 + 1 - d; { update r2 }
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end else begin
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if (q2 >= $80000000) then
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magic_add := true;
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q2 := 2*q2; { update q2 }
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r2 := 2*r2 + 1; { update r2 }
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end;
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delta := d - 1 - r2;
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until not ((p < 64) and ((q1 < delta) or ((q1 = delta) and (r1 = 0))));
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magic_m := q2 + 1; { resulting magic number }
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magic_shift := p - 32; { resulting shift }
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end;
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procedure getmagic_signed32(d : longint; out magic_m : longint; out magic_s : longint);
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const
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two_31 : DWord = high(longint)+1;
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var
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p : Longint;
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ad, anc, delta, q1, r1, q2, r2, t : DWord;
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begin
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assert((d < -1) or (d > 1));
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ad := abs(d);
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t := two_31 + (DWord(d) shr 31);
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anc := t - 1 - t mod ad; { absolute value of nc }
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p := 31; { initialize p }
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q1 := two_31 div anc; { initialize q1 = 2p/abs(nc) }
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r1 := two_31 - q1*anc; { initialize r1 = rem(2p,abs(nc)) }
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q2 := two_31 div ad; { initialize q2 = 2p/abs(d) }
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r2 := two_31 - q2*ad; { initialize r2 = rem(2p,abs(d)) }
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repeat
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inc(p);
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q1 := 2*q1; { update q1 = 2p/abs(nc) }
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r1 := 2*r1; { update r1 = rem(2p/abs(nc)) }
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if (r1 >= anc) then begin { must be unsigned comparison }
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inc(q1);
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dec(r1, anc);
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end;
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q2 := 2*q2; { update q2 = 2p/abs(d) }
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r2 := 2*r2; { update r2 = rem(2p/abs(d)) }
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if (r2 >= ad) then begin { must be unsigned comparison }
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inc(q2);
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dec(r2, ad);
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end;
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delta := ad - r2;
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until not ((q1 < delta) or ((q1 = delta) and (r1 = 0)));
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magic_m := q2 + 1;
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if (d < 0) then begin
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magic_m := -magic_m; { resulting magic number }
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end;
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magic_s := p - 32; { resulting shift }
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end;
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{$ifdef rangeon}
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{$r+}
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{$undef rangeon}
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{$endif}
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{$ifdef overflowon}
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{$q+}
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{$undef overflowon}
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{$endif}
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{*****************************************************************************
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TPPCMODDIVNODE
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*****************************************************************************}
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function tppcmoddivnode.pass_1: tnode;
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begin
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result := inherited pass_1;
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if not assigned(result) then
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include(current_procinfo.flags,pi_do_call);
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end;
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procedure tppcmoddivnode.pass_2;
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const
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{ signed overflow }
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divops: array[boolean, boolean] of tasmop =
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((A_DIVWU,A_DIVWU_),(A_DIVW,A_DIVWO_));
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zerocond: tasmcond = (dirhint: DH_Plus; simple: true; cond:C_NE; cr: RS_CR1);
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var
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power : longint;
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op : tasmop;
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numerator,
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divider,
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resultreg : tregister;
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size : Tcgsize;
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hl : tasmlabel;
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done: boolean;
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procedure genOrdConstNodeDiv;
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const
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negops : array[boolean] of tasmop = (A_NEG, A_NEGO);
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var
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magic, shift : longint;
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u_magic, u_shift : dword;
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u_add : boolean;
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divreg : tregister;
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begin
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if (tordconstnode(right).value = 0) then begin
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internalerror(2005061701);
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end else if (tordconstnode(right).value = 1) then begin
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cg.a_load_reg_reg(current_asmdata.CurrAsmList, OS_INT, OS_INT, numerator, resultreg);
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end else if (tordconstnode(right).value = -1) then begin
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// note: only in the signed case possible..., may overflow
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(negops[cs_check_overflow in aktlocalswitches], resultreg, numerator));
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end else if (ispowerof2(tordconstnode(right).value, power)) then begin
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if (is_signed(right.resulttype.def)) then begin
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{ From "The PowerPC Compiler Writer's Guide", pg. 52ff }
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SAR, OS_INT, power,
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numerator, resultreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_ADDZE, resultreg, resultreg));
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end else begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_INT, power, numerator, resultreg)
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end;
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end else begin
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{ replace division by multiplication, both implementations }
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{ from "The PowerPC Compiler Writer's Guide" pg. 53ff }
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divreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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if (is_signed(right.resulttype.def)) then begin
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getmagic_signed32(tordconstnode(right).value, magic, shift);
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// load magic value
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, magic, divreg);
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// multiply
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MULHW, resultreg, numerator, divreg));
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// add/subtract numerator
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if (tordconstnode(right).value > 0) and (magic < 0) then begin
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_ADD, OS_INT, numerator, resultreg, resultreg);
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end else if (tordconstnode(right).value < 0) and (magic > 0) then begin
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_SUB, OS_INT, numerator, resultreg, resultreg);
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end;
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// shift shift places to the right (arithmetic)
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SAR, OS_INT, shift, resultreg, resultreg);
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// extract and add sign bit
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if (tordconstnode(right).value >= 0) then begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_INT, 31, numerator, divreg);
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end else begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_INT, 31, resultreg, divreg);
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end;
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_ADD, OS_INT, resultreg, divreg, resultreg);
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end else begin
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getmagic_unsigned32(tordconstnode(right).value, u_magic, u_add, u_shift);
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// load magic in divreg
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, aint(u_magic), divreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MULHWU, resultreg, numerator, divreg));
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if (u_add) then begin
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_SUB, OS_INT, resultreg, numerator, divreg);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_INT, 1, divreg, divreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_ADD, OS_INT, divreg, resultreg, divreg);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_INT, u_shift-1, divreg, resultreg);
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end else begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_INT, u_shift, resultreg, resultreg);
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end;
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end;
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end;
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done := true;
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end;
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procedure genOrdConstNodeMod;
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var
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modreg, maskreg, tempreg : tregister;
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begin
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if (tordconstnode(right).value = 0) then begin
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internalerror(2005061702);
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end else if (abs(tordconstnode(right).value) = 1) then begin
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// x mod +/-1 is always zero
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, 0, resultreg);
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end else if (ispowerof2(tordconstnode(right).value, power)) then begin
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if (is_signed(right.resulttype.def)) then begin
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tempreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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maskreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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modreg := cg.getintregister(current_asmdata.CurrAsmList, OS_INT);
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_INT, abs(tordconstnode(right).value)-1, modreg);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SAR, OS_INT, 31, numerator, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, numerator, modreg, tempreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ANDC, maskreg, maskreg, modreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC, modreg, tempreg, 0));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBFE, modreg, modreg, modreg));
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, modreg, maskreg, maskreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_INT, maskreg, tempreg, resultreg);
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end else begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, tordconstnode(right).value-1, numerator, resultreg);
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end;
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end else begin
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genOrdConstNodeDiv();
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_MUL, OS_INT, tordconstnode(right).value, resultreg, resultreg);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_SUB, OS_INT, resultreg, numerator, resultreg);
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end;
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end;
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begin
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secondpass(left);
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secondpass(right);
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location_copy(location,left.location);
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{ put numerator in register }
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size:=def_cgsize(left.resulttype.def);
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location_force_reg(current_asmdata.CurrAsmList,left.location,
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size,true);
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location_copy(location,left.location);
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numerator := location.register;
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resultreg := location.register;
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if (location.loc = LOC_CREGISTER) then begin
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location.loc := LOC_REGISTER;
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location.register := cg.getintregister(current_asmdata.CurrAsmList,size);
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resultreg := location.register;
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end else if (nodetype = modn) or (right.nodetype = ordconstn) then begin
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// for a modulus op, and for const nodes we need the result register
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// to be an extra register
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resultreg := cg.getintregister(current_asmdata.CurrAsmList,size);
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end;
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done := false;
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if (right.nodetype = ordconstn) then begin
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if (nodetype = divn) then
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genOrdConstNodeDiv
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else
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genOrdConstNodeMod;
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done := true;
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end;
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if (not done) then begin
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{ load divider in a register if necessary }
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location_force_reg(current_asmdata.CurrAsmList,right.location,
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def_cgsize(right.resulttype.def),true);
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if (right.nodetype <> ordconstn) then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_CMPWI,NR_CR1,
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right.location.register,0));
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divider := right.location.register;
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{ needs overflow checking, (-maxlongint-1) div (-1) overflows! }
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op := divops[is_signed(right.resulttype.def),
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cs_check_overflow in aktlocalswitches];
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,resultreg,numerator,
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divider));
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if (nodetype = modn) then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MULLW,resultreg,
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divider,resultreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUB,location.register,
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numerator,resultreg));
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resultreg := location.register;
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end;
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end;
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{ set result location }
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location.loc:=LOC_REGISTER;
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location.register:=resultreg;
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if right.nodetype <> ordconstn then
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begin
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current_asmdata.getjumplabel(hl);
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current_asmdata.CurrAsmList.concat(taicpu.op_cond_sym(A_BC,zerocond,hl));
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_DIVBYZERO');
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cg.a_label(current_asmdata.CurrAsmList,hl);
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end;
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{ unsigned division/module can only overflow in case of division by zero }
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{ (but checking this overflow flag is more convoluted than performing a }
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{ simple comparison with 0) }
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if is_signed(right.resulttype.def) then
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cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resulttype.def);
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end;
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{*****************************************************************************
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TPPCSHLRSHRNODE
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*****************************************************************************}
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function tppcshlshrnode.first_shlshr64bitint: tnode;
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begin
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result := nil;
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end;
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|
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procedure tppcshlshrnode.pass_2;
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var
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resultreg, hregister1,hregister2,
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hreg64hi,hreg64lo : tregister;
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op : topcg;
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asmop1, asmop2: tasmop;
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shiftval: aint;
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begin
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secondpass(left);
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secondpass(right);
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if is_64bitint(left.resulttype.def) then
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begin
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location_force_reg(current_asmdata.CurrAsmList,left.location,
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def_cgsize(left.resulttype.def),true);
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location_copy(location,left.location);
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hreg64hi := location.register64.reghi;
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hreg64lo := location.register64.reglo;
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if (location.loc = LOC_CREGISTER) then
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begin
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location.loc := LOC_REGISTER;
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location.register64.reghi := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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location.register64.reglo := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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end;
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if (right.nodetype = ordconstn) then
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begin
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shiftval := tordconstnode(right).value;
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shiftval := shiftval and 63;
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{
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I think the statements below is much more correct instead of the hack above,
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but then we fail tshlshr.pp :/
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if shiftval > 63 then
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begin
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,location.register64.reglo);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,location.register64.reglo);
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end
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else } if shiftval > 31 then
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begin
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if nodetype = shln then
|
|
begin
|
|
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,
|
|
shiftval and 31,hreg64lo,location.register64.reghi);
|
|
cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,location.register64.reglo);
|
|
end
|
|
else
|
|
begin
|
|
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,
|
|
shiftval and 31,hreg64hi,location.register64.reglo);
|
|
cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,location.register64.reghi);
|
|
end;
|
|
end
|
|
else
|
|
begin
|
|
if nodetype = shln then
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const_const_const(
|
|
A_RLWINM,location.register64.reghi,hreg64hi,shiftval,
|
|
0,31-shiftval));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const_const_const(
|
|
A_RLWIMI,location.register64.reghi,hreg64lo,shiftval,
|
|
32-shiftval,31));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const_const_const(
|
|
A_RLWINM,location.register64.reglo,hreg64lo,shiftval,
|
|
0,31-shiftval));
|
|
end
|
|
else
|
|
begin
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const_const_const(
|
|
A_RLWINM,location.register64.reglo,hreg64lo,32-shiftval,
|
|
shiftval,31));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const_const_const(
|
|
A_RLWIMI,location.register64.reglo,hreg64hi,32-shiftval,
|
|
0,shiftval-1));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const_const_const(
|
|
A_RLWINM,location.register64.reghi,hreg64hi,32-shiftval,
|
|
shiftval,31));
|
|
end;
|
|
end;
|
|
end
|
|
else
|
|
{ no constant shiftcount }
|
|
begin
|
|
location_force_reg(current_asmdata.CurrAsmList,right.location,OS_S32,true);
|
|
hregister1 := right.location.register;
|
|
if nodetype = shln then
|
|
begin
|
|
asmop1 := A_SLW;
|
|
asmop2 := A_SRW;
|
|
end
|
|
else
|
|
begin
|
|
asmop1 := A_SRW;
|
|
asmop2 := A_SLW;
|
|
resultreg := hreg64hi;
|
|
hreg64hi := hreg64lo;
|
|
hreg64lo := resultreg;
|
|
resultreg := location.register64.reghi;
|
|
location.register64.reghi := location.register64.reglo;
|
|
location.register64.reglo := resultreg;
|
|
end;
|
|
|
|
cg.getcpuregister(current_asmdata.CurrAsmList,NR_R0);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC,
|
|
NR_R0,hregister1,32));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(asmop1,
|
|
location.register64.reghi,hreg64hi,hregister1));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(asmop2,
|
|
NR_R0,hreg64lo,NR_R0));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_OR,
|
|
location.register64.reghi,location.register64.reghi,NR_R0));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBI,
|
|
NR_R0,hregister1,32));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(asmop1,
|
|
NR_R0,hreg64lo,NR_R0));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_OR,
|
|
location.register64.reghi,location.register64.reghi,NR_R0));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(asmop1,
|
|
location.register64.reglo,hreg64lo,hregister1));
|
|
cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_R0);
|
|
|
|
if nodetype = shrn then
|
|
begin
|
|
resultreg := location.register64.reghi;
|
|
location.register64.reghi := location.register64.reglo;
|
|
location.register64.reglo := resultreg;
|
|
end;
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
{ load left operators in a register }
|
|
location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resulttype.def),true);
|
|
location_copy(location,left.location);
|
|
resultreg := location.register;
|
|
hregister1 := location.register;
|
|
if (location.loc = LOC_CREGISTER) then
|
|
begin
|
|
location.loc := LOC_REGISTER;
|
|
resultreg := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
location.register := resultreg;
|
|
end;
|
|
|
|
{ determine operator }
|
|
if nodetype=shln then
|
|
op:=OP_SHL
|
|
else
|
|
op:=OP_SHR;
|
|
|
|
{ shifting by a constant directly coded: }
|
|
if (right.nodetype=ordconstn) then
|
|
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,OS_32,
|
|
tordconstnode(right).value and 31,hregister1,resultreg)
|
|
else
|
|
begin
|
|
{ load shift count in a register if necessary }
|
|
location_force_reg(current_asmdata.CurrAsmList,right.location,def_cgsize(right.resulttype.def),true);
|
|
hregister2 := right.location.register;
|
|
|
|
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,OS_32,hregister2,
|
|
hregister1,resultreg);
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
TPPCUNARYMINUSNODE
|
|
*****************************************************************************}
|
|
|
|
procedure tppcunaryminusnode.pass_2;
|
|
|
|
var
|
|
src1: tregister;
|
|
op: tasmop;
|
|
|
|
begin
|
|
secondpass(left);
|
|
if is_64bitint(left.resulttype.def) then
|
|
begin
|
|
location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resulttype.def),true);
|
|
location_copy(location,left.location);
|
|
if (location.loc = LOC_CREGISTER) then
|
|
begin
|
|
location.register64.reglo := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
location.register64.reghi := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
location.loc := LOC_REGISTER;
|
|
end;
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SUBFIC,
|
|
location.register64.reglo,left.location.register64.reglo,0));
|
|
if not(cs_check_overflow in aktlocalswitches) then
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_SUBFZE,
|
|
location.register64.reghi,left.location.register64.reghi))
|
|
else
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_SUBFZEO_,
|
|
location.register64.reghi,left.location.register64.reghi));
|
|
end
|
|
else
|
|
begin
|
|
location_copy(location,left.location);
|
|
location.loc:=LOC_REGISTER;
|
|
case left.location.loc of
|
|
LOC_FPUREGISTER, LOC_REGISTER:
|
|
begin
|
|
src1 := left.location.register;
|
|
location.register := src1;
|
|
end;
|
|
LOC_CFPUREGISTER, LOC_CREGISTER:
|
|
begin
|
|
src1 := left.location.register;
|
|
if left.location.loc = LOC_CREGISTER then
|
|
location.register := cg.getintregister(current_asmdata.CurrAsmList,OS_INT)
|
|
else
|
|
location.register := cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
|
|
end;
|
|
LOC_REFERENCE,LOC_CREFERENCE:
|
|
begin
|
|
if (left.resulttype.def.deftype=floatdef) then
|
|
begin
|
|
src1 := cg.getfpuregister(current_asmdata.CurrAsmList,def_cgsize(left.resulttype.def));
|
|
location.register := src1;
|
|
cg.a_loadfpu_ref_reg(current_asmdata.CurrAsmList,
|
|
def_cgsize(left.resulttype.def),
|
|
left.location.reference,src1);
|
|
end
|
|
else
|
|
begin
|
|
src1 := cg.getintregister(current_asmdata.CurrAsmList,OS_32);
|
|
location.register:= src1;
|
|
cg.a_load_ref_reg(current_asmdata.CurrAsmList,OS_32,OS_32,
|
|
left.location.reference,src1);
|
|
end;
|
|
end;
|
|
end;
|
|
{ choose appropriate operand }
|
|
if left.resulttype.def.deftype <> floatdef then
|
|
begin
|
|
if not(cs_check_overflow in aktlocalswitches) then
|
|
op := A_NEG
|
|
else
|
|
op := A_NEGO_;
|
|
location.loc := LOC_REGISTER;
|
|
end
|
|
else
|
|
begin
|
|
op := A_FNEG;
|
|
location.loc := LOC_FPUREGISTER;
|
|
end;
|
|
{ emit operation }
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,location.register,src1));
|
|
end;
|
|
{ Here was a problem... }
|
|
{ Operand to be negated always }
|
|
{ seems to be converted to signed }
|
|
{ 32-bit before doing neg!! }
|
|
{ So this is useless... }
|
|
{ that's not true: -2^31 gives an overflow error if it is negated (FK) }
|
|
cg.g_overflowcheck(current_asmdata.CurrAsmList,location,resulttype.def);
|
|
end;
|
|
|
|
|
|
{*****************************************************************************
|
|
TPPCNOTNODE
|
|
*****************************************************************************}
|
|
|
|
procedure tppcnotnode.pass_2;
|
|
|
|
var
|
|
hl : tasmlabel;
|
|
|
|
begin
|
|
if is_boolean(resulttype.def) then
|
|
begin
|
|
{ if the location is LOC_JUMP, we do the secondpass after the
|
|
labels are allocated
|
|
}
|
|
if left.expectloc=LOC_JUMP then
|
|
begin
|
|
hl:=current_procinfo.CurrTrueLabel;
|
|
current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
|
|
current_procinfo.CurrFalseLabel:=hl;
|
|
secondpass(left);
|
|
maketojumpbool(current_asmdata.CurrAsmList,left,lr_load_regvars);
|
|
hl:=current_procinfo.CurrTrueLabel;
|
|
current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
|
|
current_procinfo.CurrFalseLabel:=hl;
|
|
location.loc:=LOC_JUMP;
|
|
end
|
|
else
|
|
begin
|
|
secondpass(left);
|
|
case left.location.loc of
|
|
LOC_FLAGS :
|
|
begin
|
|
location_copy(location,left.location);
|
|
inverse_flags(location.resflags);
|
|
end;
|
|
LOC_REGISTER, LOC_CREGISTER, LOC_REFERENCE, LOC_CREFERENCE :
|
|
begin
|
|
location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resulttype.def),true);
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMPWI,left.location.register,0));
|
|
location_reset(location,LOC_FLAGS,OS_NO);
|
|
location.resflags.cr:=RS_CR0;
|
|
location.resflags.flag:=F_EQ;
|
|
end;
|
|
else
|
|
internalerror(2003042401);
|
|
end;
|
|
end;
|
|
end
|
|
else if is_64bitint(left.resulttype.def) then
|
|
begin
|
|
secondpass(left);
|
|
location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resulttype.def),false);
|
|
location_copy(location,left.location);
|
|
{ perform the NOT operation }
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_NOT,location.register64.reghi,
|
|
location.register64.reghi));
|
|
current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_NOT,location.register64.reglo,
|
|
location.register64.reglo));
|
|
end
|
|
else
|
|
begin
|
|
secondpass(left);
|
|
location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resulttype.def),true);
|
|
location_copy(location,left.location);
|
|
location.loc := LOC_REGISTER;
|
|
location.register := cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
|
|
{ perform the NOT operation }
|
|
cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NOT,def_cgsize(resulttype.def),left.location.register,
|
|
location.register);
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
cmoddivnode:=tppcmoddivnode;
|
|
cshlshrnode:=tppcshlshrnode;
|
|
cunaryminusnode:=tppcunaryminusnode;
|
|
cnotnode:=tppcnotnode;
|
|
end.
|