.. |
aasmcpu.pas
|
Also disable overflow where range check is disabled in aasmcpu unit
|
2015-02-24 15:58:49 +00:00 |
agx86att.pas
|
+ iphonesim/x86_64 target (64 bit iOS simulator)
|
2015-02-23 22:56:09 +00:00 |
agx86int.pas
|
* fix assembling with masm according to #25858
|
2015-02-05 21:22:39 +00:00 |
agx86nsm.pas
|
+ support section smartlinking with nasm
|
2015-02-08 12:33:50 +00:00 |
cga.pas
|
+ support for FMA intrinsic: if there is no hardware support, the compiler throws an error.
|
2014-04-13 19:21:54 +00:00 |
cgx86.pas
|
* moved x86-specific requirements from the generic bsr/bsf code to the
|
2015-02-23 22:57:18 +00:00 |
cpubase.pas
|
+ Implemented IEEE 754-compliant checking for unordered results of floating-point compares on x86 targets. Mantis #9362.
|
2014-04-14 12:36:11 +00:00 |
hlcgx86.pas
|
|
|
itcpugas.pas
|
|
|
itx86int.pas
|
|
|
ni86mem.pas
|
* isolated segment-related functionality of tabsolutevarsym into i386/i8086-
|
2014-03-30 15:42:53 +00:00 |
nx86add.pas
|
x86: fix a variable op not initialized warning. This hopefully fixes our x86 testsuite run.
|
2014-08-20 10:21:06 +00:00 |
nx86cal.pas
|
* a_call_ref functionality cannot be implemented efficiently at code generator level, because references need specific preparations at earlier points. Moved this support to tcgcallnode and its x86 descendants, and got rid of all ifdef's around.
|
2014-02-03 13:28:56 +00:00 |
nx86cnv.pas
|
* x86: improve x87 qword to float conversion, using single-precision constants saves space and removes need in separate load on FPU stack. No precision loss occurs because 2**64 is representable exactly even in single precision.
|
2014-03-03 20:41:42 +00:00 |
nx86con.pas
|
|
|
nx86inl.pas
|
+ cpu capability CPUX86_HAS_CMOV
|
2015-02-21 20:47:40 +00:00 |
nx86mat.pas
|
* make integer division instruction (div/idiv) on x86 dependent on the
|
2015-01-04 13:08:57 +00:00 |
nx86mem.pas
|
* generic part of r26050 from the hlcgllvm branch: made tcgvecnode hlcg-safe
|
2015-02-23 22:56:00 +00:00 |
nx86set.pas
|
* Use GOT-relative constants for i386 PIC jump tables, they don't need runtime relocations. Now almost ABI-compliant on Linux/BSD (Darwin targets unchanged). Also clean up i8086-specific stuff: using tai_const.create_type_sym(aitconst_ptr,...) generates near pointers on i8086, which is the desired goal.
|
2014-03-03 21:06:49 +00:00 |
rax86.pas
|
- x86 assembler readers: cleaned out operand swapping code. Operands of TInstruction are kept in AT&T order, Intel reader attaches operands right-to-left. It was effectively the same way before the change (except Intel reader attaching operands left-to-right, followed by a single swap), operand order checks all over the place were just reducing readability.
|
2014-11-16 16:37:26 +00:00 |
rax86att.pas
|
- x86 assembler readers: cleaned out operand swapping code. Operands of TInstruction are kept in AT&T order, Intel reader attaches operands right-to-left. It was effectively the same way before the change (except Intel reader attaching operands left-to-right, followed by a single swap), operand order checks all over the place were just reducing readability.
|
2014-11-16 16:37:26 +00:00 |
rax86int.pas
|
+ applied remaining patches of Torsten Grundke: adds gather instructions of avx2
|
2015-02-17 21:43:46 +00:00 |
rgx86.pas
|
* Put under {$ifndef x86_64} more cases of instructions that do not exist in 64-bit mode.
|
2014-06-11 12:51:38 +00:00 |
symi86.pas
|
* i8086 and i386-specific code from tabstractprocdef.is_pushleftright moved to
|
2014-04-12 15:34:08 +00:00 |
symx86.pas
|
* reimplemented r28329 in a different way, as suggested by Jonas
|
2014-08-07 19:36:52 +00:00 |
x86ins.dat
|
+ applied remaining patches of Torsten Grundke: adds gather instructions of avx2
|
2015-02-17 21:43:46 +00:00 |
x86reg.dat
|
* x86 targets: Profiling shows that quite a bit of time is spent in findreg_by_number(), despite it uses binary search. Worse, it is repeated for every piece of register information. Trying to get rid of some of these calls: rearranged registers so that their "opcode" matches 3 LSBs of superregister number (with a few exceptions described at the beginning of x86reg.dat). This allows to lookup opcodes in regval() with O(1) complexity, and removes need in rXXXop.inc files.
|
2013-10-03 08:08:04 +00:00 |