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333 lines
13 KiB
ObjectPascal
333 lines
13 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate SPARC assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncpumat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat;
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type
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tSparcmoddivnode = class(tmoddivnode)
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procedure pass_generate_code;override;
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end;
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tSparcshlshrnode = class(tshlshrnode)
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procedure pass_generate_code;override;
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{ everything will be handled in pass_2 }
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function first_shlshr64bitint: tnode; override;
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end;
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tSparcnotnode = class(tcgnotnode)
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procedure second_boolean;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,
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aasmbase,aasmcpu,aasmtai,aasmdata,
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defutil,
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cgbase,cgobj,pass_2,procinfo,
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ncon,
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cpubase,
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ncgutil,cgcpu,cgutils;
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{*****************************************************************************
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TSparcMODDIVNODE
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*****************************************************************************}
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procedure tSparcmoddivnode.pass_generate_code;
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const
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{ signed overflow }
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divops: array[boolean, boolean] of tasmop =
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((A_UDIV,A_UDIVcc),(A_SDIV,A_SDIVcc));
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var
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power : longint;
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op : tasmop;
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tmpreg,
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numerator,
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divider,
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resultreg : tregister;
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overflowlabel : tasmlabel;
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ai : taicpu;
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begin
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secondpass(left);
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secondpass(right);
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location_copy(location,left.location);
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{ put numerator in register }
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resultdef),true);
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location_copy(location,left.location);
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numerator := location.register;
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if (nodetype = modn) then
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resultreg := cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT)
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else
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begin
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if (location.loc = LOC_CREGISTER) then
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begin
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location.loc := LOC_REGISTER;
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location.register := cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
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end;
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resultreg := location.register;
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end;
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if (nodetype = divn) and
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(right.nodetype = ordconstn) and
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ispowerof2(tordconstnode(right).value,power) then
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begin
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if is_signed(left.resultdef) Then
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begin
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tmpreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,OS_INT,31,numerator,tmpreg);
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{ if signed, tmpreg=right value-1, otherwise 0 }
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,OS_INT,tordconstnode(right).value-1,tmpreg);
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{ add to the left value }
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_ADD,OS_INT,tmpreg,numerator);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,OS_INT,aword(power),numerator,resultreg);
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end
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_INT,aword(power),numerator,resultreg);
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end
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else
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begin
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{ load divider in a register if necessary }
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location_force_reg(current_asmdata.CurrAsmList,right.location,
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def_cgsize(right.resultdef),true);
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divider := right.location.register;
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{ needs overflow checking, (-maxlongint-1) div (-1) overflows! }
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{ And on Sparc, the only way to catch a div-by-0 is by checking }
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{ the overflow flag (JM) }
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{ Fill %y with the -1 or 0 depending on the highest bit }
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if is_signed(left.resultdef) then
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begin
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tmpreg:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const_reg(A_SRA,numerator,31,tmpreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_MOV,tmpreg,NR_Y));
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_MOV,NR_G0,NR_Y));
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{ wait 3 instructions slots before we can read %y }
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current_asmdata.CurrAsmList.concat(taicpu.op_none(A_NOP));
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current_asmdata.CurrAsmList.concat(taicpu.op_none(A_NOP));
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current_asmdata.CurrAsmList.concat(taicpu.op_none(A_NOP));
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op := divops[is_signed(right.resultdef),
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cs_check_overflow in current_settings.localswitches];
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,numerator,divider,resultreg));
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if (nodetype = modn) then
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begin
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current_asmdata.getjumplabel(overflowlabel);
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ai:=taicpu.op_cond_sym(A_Bxx,C_O,overflowlabel);
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ai.delayslot_annulled:=true;
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current_asmdata.CurrAsmList.concat(ai);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg(A_NOT,resultreg));
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cg.a_label(current_asmdata.CurrAsmList,overflowlabel);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SMUL,resultreg,divider,resultreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUB,numerator,resultreg,resultreg));
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end;
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end;
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{ set result location }
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location.loc:=LOC_REGISTER;
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location.register:=resultreg;
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cg.g_overflowcheck(current_asmdata.CurrAsmList,Location,resultdef);
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end;
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{*****************************************************************************
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TSparcSHLRSHRNODE
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*****************************************************************************}
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function TSparcShlShrNode.first_shlshr64bitint:TNode;
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begin
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{ 64bit without constants need a helper }
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if is_64bit(left.resultdef) and
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(right.nodetype<>ordconstn) then
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begin
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result:=inherited first_shlshr64bitint;
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exit;
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end;
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result := nil;
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end;
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procedure tSparcshlshrnode.pass_generate_code;
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var
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hregister,resultreg,hregister1,
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hreg64hi,hreg64lo : tregister;
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op : topcg;
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shiftval: aword;
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begin
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{ 64bit without constants need a helper, and is
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already replaced in pass1 }
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if is_64bit(left.resultdef) and
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(right.nodetype<>ordconstn) then
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internalerror(200405301);
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secondpass(left);
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secondpass(right);
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if is_64bit(left.resultdef) then
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begin
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location_reset(location,LOC_REGISTER,OS_64);
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{ load left operator in a register }
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location_force_reg(current_asmdata.CurrAsmList,left.location,OS_64,false);
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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shiftval := tordconstnode(right).value and 63;
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if shiftval > 31 then
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begin
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if nodetype = shln then
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begin
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,hreg64hi);
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if (shiftval and 31) <> 0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,shiftval and 31,hreg64lo,hreg64lo);
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end
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else
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begin
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,hreg64lo);
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if (shiftval and 31) <> 0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,shiftval and 31,hreg64hi,hreg64hi);
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end;
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location.register64.reglo:=hreg64hi;
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location.register64.reghi:=hreg64lo;
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end
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else
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begin
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hregister:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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if nodetype = shln then
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,32-shiftval,hreg64lo,hregister);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,shiftval,hreg64hi,hreg64hi);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,hregister,hreg64hi,hreg64hi);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,shiftval,hreg64lo,hreg64lo);
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end
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else
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHL,OS_32,32-shiftval,hreg64hi,hregister);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,shiftval,hreg64lo,hreg64lo);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_OR,OS_32,hregister,hreg64lo,hreg64lo);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_32,shiftval,hreg64hi,hreg64hi);
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end;
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location.register64.reghi:=hreg64hi;
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location.register64.reglo:=hreg64lo;
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end;
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end
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else
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begin
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{ load left operators in a register }
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resultdef),true);
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location_copy(location,left.location);
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resultreg := location.register;
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hregister1 := location.register;
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if (location.loc = LOC_CREGISTER) then
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begin
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location.loc := LOC_REGISTER;
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resultreg := cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
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location.register := resultreg;
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end;
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{ determine operator }
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if nodetype=shln then
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op:=OP_SHL
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else
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op:=OP_SHR;
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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begin
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if tordconstnode(right).value and 31<>0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,OS_32,tordconstnode(right).value and 31,hregister1,resultreg)
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end
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else
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begin
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{ load shift count in a register if necessary }
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location_force_reg(current_asmdata.CurrAsmList,right.location,def_cgsize(right.resultdef),true);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,OS_32,right.location.register,hregister1,resultreg);
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end;
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end;
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end;
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{*****************************************************************************
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TSPARCNOTNODE
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*****************************************************************************}
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procedure tsparcnotnode.second_boolean;
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var
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hl : tasmlabel;
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begin
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{ if the location is LOC_JUMP, we do the secondpass after the
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labels are allocated
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}
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if left.expectloc=LOC_JUMP then
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begin
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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secondpass(left);
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maketojumpbool(current_asmdata.CurrAsmList,left,lr_load_regvars);
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hl:=current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel:=current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel:=hl;
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location.loc:=LOC_JUMP;
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end
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else
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begin
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secondpass(left);
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case left.location.loc of
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LOC_FLAGS :
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begin
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location_copy(location,left.location);
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inverse_flags(location.resflags);
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end;
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LOC_REGISTER, LOC_CREGISTER,
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LOC_REFERENCE, LOC_CREFERENCE,
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LOC_SUBSETREG, LOC_CSUBSETREG,
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LOC_SUBSETREF, LOC_CSUBSETREF:
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begin
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location_force_reg(current_asmdata.CurrAsmList,left.location,def_cgsize(left.resultdef),true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const_reg(A_SUBcc,left.location.register,0,NR_G0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_E;
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end;
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else
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internalerror(2003042401);
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end;
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end;
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end;
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begin
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cmoddivnode:=tSparcmoddivnode;
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cshlshrnode:=tSparcshlshrnode;
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cnotnode:=tSparcnotnode;
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end.
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