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https://gitlab.com/freepascal.org/fpc/source.git
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352 lines
12 KiB
ObjectPascal
352 lines
12 KiB
ObjectPascal
{
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David Zhang 2007/01/15
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$Id: ncpumat.pas,v 1.23 2005/02/14 17:13:10 peter Exp $
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate MIPSel assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncpumat;
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{$i fpcdefs.inc}
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interface
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uses
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node, nmat, ncgmat, cgbase;
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type
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tMIPSELmoddivnode = class(tmoddivnode)
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procedure pass_generate_code;override;
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end;
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tMIPSELshlshrnode = class(tshlshrnode)
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procedure pass_generate_code;override;
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{ everything will be handled in pass_2 }
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function first_shlshr64bitint: tnode; override;
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end;
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tMIPSELnotnode = class(tcgnotnode)
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procedure second_boolean; override;
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end;
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TMIPSunaryminusnode = class(tcgunaryminusnode)
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procedure emit_float_sign_change(r: tregister; _size : tcgsize);override;
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end;
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implementation
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uses
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globtype, systems,
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cutils, verbose, globals,
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symconst, symdef,
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aasmbase, aasmcpu, aasmtai, aasmdata,
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defutil,
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procinfo,
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cgobj, hlcgobj, pass_2,
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ncon,
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cpubase,
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ncgutil, cgcpu, cgutils;
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{*****************************************************************************
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TMipselMODDIVNODE
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*****************************************************************************}
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procedure tMIPSELmoddivnode.pass_generate_code;
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var
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power: longint;
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tmpreg, numerator, divider, resultreg: tregister;
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begin
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secondpass(left);
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secondpass(right);
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location_copy(location, left.location);
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{ put numerator in register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList, left.location, left.resultdef, left.resultdef, True);
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location_copy(location, left.location);
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numerator := location.Register;
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if (nodetype = modn) then
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resultreg := cg.GetIntRegister(current_asmdata.CurrAsmList, OS_INT)
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else
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begin
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if (location.loc = LOC_CREGISTER) then
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begin
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location.loc := LOC_REGISTER;
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location.Register := cg.GetIntRegister(current_asmdata.CurrAsmList, OS_INT);
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end;
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resultreg := location.Register;
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end;
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if (nodetype = divn) and
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(right.nodetype = ordconstn) and
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ispowerof2(tordconstnode(right).Value.svalue, power) then
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begin
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tmpreg := cg.GetIntRegister(current_asmdata.CurrAsmList, OS_INT);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SAR, OS_INT, 31, numerator, tmpreg);
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{ if signed, tmpreg=right value-1, otherwise 0 }
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cg.a_op_const_reg(current_asmdata.CurrAsmList, OP_AND, OS_INT, tordconstnode(right).Value.svalue - 1, tmpreg);
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{ add to the left value }
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cg.a_op_reg_reg(current_asmdata.CurrAsmList, OP_ADD, OS_INT, tmpreg, numerator);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SAR, OS_INT, aword(power), numerator, resultreg);
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end
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else
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begin
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{ load divider in a register if necessary }
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hlcg.location_force_reg(current_asmdata.CurrAsmList, right.location,
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right.resultdef, right.resultdef, True);
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divider := right.location.Register;
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if (nodetype = modn) then
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begin
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if is_signed(right.resultdef) then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_REM, resultreg, numerator, divider));
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_REMU, resultreg, numerator, divider));
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end
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else
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begin
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if is_signed({left.resultdef}right.resultdef) then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_DIV, resultreg, numerator, divider));
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_DIVU, resultreg, numerator, divider));
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end;
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end;
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{ set result location }
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location.loc := LOC_REGISTER;
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location.Register := resultreg;
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end;
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{*****************************************************************************
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TMIPSelSHLRSHRNODE
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*****************************************************************************}
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function TMIPSELShlShrNode.first_shlshr64bitint: TNode;
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begin
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{ 64bit without constants need a helper }
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if is_64bit(left.resultdef) and
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(right.nodetype <> ordconstn) then
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begin
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Result := inherited first_shlshr64bitint;
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exit;
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end;
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Result := nil;
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end;
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procedure tMIPSELshlshrnode.pass_generate_code;
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var
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hregister, resultreg, hregister1, hreg64hi, hreg64lo: tregister;
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op: topcg;
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shiftval: aword;
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begin
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{ 64bit without constants need a helper, and is
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already replaced in pass1 }
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if is_64bit(left.resultdef) and
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(right.nodetype <> ordconstn) then
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internalerror(200405301);
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secondpass(left);
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secondpass(right);
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if is_64bit(left.resultdef) then
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begin
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location_reset(location, LOC_REGISTER, OS_64);
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{ load left operator in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList, left.location, left.resultdef, u64inttype, False);
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hreg64hi := left.location.register64.reghi;
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hreg64lo := left.location.register64.reglo;
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shiftval := tordconstnode(right).Value.svalue and 63;
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if shiftval > 31 then
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begin
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if nodetype = shln then
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begin
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_32, 0, hreg64hi);
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if (shiftval and 31) <> 0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, shiftval and 31, hreg64lo, hreg64lo);
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end
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else
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begin
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cg.a_load_const_reg(current_asmdata.CurrAsmList, OS_32, 0, hreg64lo);
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if (shiftval and 31) <> 0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, shiftval and 31, hreg64hi, hreg64hi);
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end;
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location.register64.reglo := hreg64hi;
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location.register64.reghi := hreg64lo;
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end
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else
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begin
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if shiftval <> 0 then
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begin
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hregister := cg.getintregister(current_asmdata.CurrAsmList, OS_32);
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if nodetype = shln then
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, 32 - shiftval, hreg64lo, hregister);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, shiftval, hreg64hi, hreg64hi);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_32, hregister, hreg64hi, hreg64hi);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, shiftval, hreg64lo, hreg64lo);
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end
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else
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begin
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHL, OS_32, 32 - shiftval, hreg64hi, hregister);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, shiftval, hreg64lo, hreg64lo);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, OP_OR, OS_32, hregister, hreg64lo, hreg64lo);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, OP_SHR, OS_32, shiftval, hreg64hi, hreg64hi);
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end;
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end;
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location.register64.reghi := hreg64hi;
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location.register64.reglo := hreg64lo;
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end;
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end
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else
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begin
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{ load left operators in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList, left.location, left.resultdef, left.resultdef, True);
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location_copy(location, left.location);
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resultreg := location.Register;
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hregister1 := location.Register;
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if (location.loc = LOC_CREGISTER) then
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begin
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location.loc := LOC_REGISTER;
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resultreg := cg.GetIntRegister(current_asmdata.CurrAsmList, OS_INT);
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location.Register := resultreg;
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end;
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{ determine operator }
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if nodetype = shln then
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op := OP_SHL
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else
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op := OP_SHR;
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{ shifting by a constant directly coded: }
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if (right.nodetype = ordconstn) then
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begin
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if tordconstnode(right).Value.svalue and 31 <> 0 then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList, op, OS_32, tordconstnode(right).Value.svalue and 31, hregister1, resultreg);
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end
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else
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begin
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{ load shift count in a register if necessary }
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hlcg.location_force_reg(current_asmdata.CurrAsmList, right.location, right.resultdef, right.resultdef, True);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList, op, OS_32, right.location.Register, hregister1, resultreg);
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end;
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end;
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end;
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{*****************************************************************************
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TMIPSelNOTNODE
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*****************************************************************************}
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procedure tMIPSELnotnode.second_boolean;
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var
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hl: tasmlabel;
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tmpreg : TRegister;
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r64: TRegister64;
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begin
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{ if the location is LOC_JUMP, we do the secondpass after the
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labels are allocated
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}
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if left.expectloc = LOC_JUMP then
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begin
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hl := current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel := current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel := hl;
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secondpass(left);
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maketojumpbool(current_asmdata.CurrAsmList, left, lr_load_regvars);
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hl := current_procinfo.CurrTrueLabel;
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current_procinfo.CurrTrueLabel := current_procinfo.CurrFalseLabel;
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current_procinfo.CurrFalseLabel := hl;
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location.loc := LOC_JUMP;
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end
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else
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begin
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secondpass(left);
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case left.location.loc of
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LOC_REGISTER, LOC_CREGISTER, LOC_REFERENCE, LOC_CREFERENCE,
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LOC_SUBSETREG,LOC_CSUBSETREG,LOC_SUBSETREF,LOC_CSUBSETREF:
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList, left.location, left.resultdef, left.resultdef, True);
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if is_64bit(resultdef) then
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begin
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r64.reglo:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
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r64.reghi:=cg.GetIntRegister(current_asmdata.CurrAsmList,OS_INT);
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{ OR low and high parts together }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_OR,r64.reglo,left.location.register64.reglo,left.location.register64.reghi));
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{ x=0 <=> unsigned(x)<1 }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SLTIU,r64.reglo,r64.reglo,1));
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if is_cbool(resultdef) then
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begin
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NEG,OS_S32,r64.reglo,r64.reglo);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,OS_32,OS_32,r64.reglo,r64.reghi);
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end
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else
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cg.a_load_const_reg(current_asmdata.CurrAsmList,OS_32,0,r64.reghi);
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location_reset(location,LOC_REGISTER,OS_64);
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location.Register64:=r64;
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end
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else
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begin
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tmpreg := cg.GetIntRegister(current_asmdata.CurrAsmList, OS_INT);
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{ x=0 <=> unsigned(x)<1 }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_SLTIU, tmpreg, left.location.Register, 1));
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if is_cbool(resultdef) then
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NEG,OS_S32,tmpreg,tmpreg);
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location_reset(location, LOC_REGISTER, OS_INT);
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location.Register := tmpreg;
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end;
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end;
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else
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internalerror(2003042401);
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end;
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end;
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end;
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{*****************************************************************************
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TMIPSunaryminusnode
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*****************************************************************************}
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procedure TMIPSunaryminusnode.emit_float_sign_change(r: tregister; _size : tcgsize);
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begin
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case _size of
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OS_F32:
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_NEG_s,r,r));
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OS_F64:
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_NEG_d,r,r));
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else
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internalerror(2013030501);
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end;
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end;
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begin
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cmoddivnode := tMIPSELmoddivnode;
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cshlshrnode := tMIPSELshlshrnode;
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cnotnode := tMIPSELnotnode;
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cunaryminusnode := TMIPSunaryminusnode;
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end.
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