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https://gitlab.com/freepascal.org/fpc/source.git
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795 lines
30 KiB
ObjectPascal
795 lines
30 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl and Jonas Maebe
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This unit contains the peephole optimizer for i386
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit aoptcpu;
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{$i fpcdefs.inc}
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{ $define DEBUG_AOPTCPU}
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Interface
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uses
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cgbase,
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cpubase, aopt, aoptx86,
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Aasmbase,aasmtai,aasmdata;
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Type
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TCpuAsmOptimizer = class(TX86AsmOptimizer)
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procedure Optimize; override;
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procedure PrePeepHoleOpts; override;
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procedure PeepHoleOptPass1; override;
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procedure PeepHoleOptPass2; override;
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procedure PostPeepHoleOpts; override;
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end;
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Var
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AsmOptimizer : TCpuAsmOptimizer;
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Implementation
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uses
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verbose,globtype,globals,
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cpuinfo,
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aasmcpu,
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aoptutils,
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procinfo,
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cgutils,
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{ units we should get rid off: }
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symsym,symconst;
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{ Checks if the register is a 32 bit general purpose register }
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function isgp32reg(reg: TRegister): boolean;
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begin
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{$push}{$warnings off}
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isgp32reg:=(getregtype(reg)=R_INTREGISTER) and (getsupreg(reg)>=RS_EAX) and (getsupreg(reg)<=RS_EBX);
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{$pop}
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end;
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{ returns true if p contains a memory operand with a segment set }
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function InsContainsSegRef(p: taicpu): boolean;
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var
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i: longint;
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begin
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result:=true;
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for i:=0 to p.opercnt-1 do
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if (p.oper[i]^.typ=top_ref) and
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(p.oper[i]^.ref^.segment<>NR_NO) then
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exit;
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result:=false;
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end;
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procedure TCPUAsmOptimizer.PrePeepHoleOpts;
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var
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p: tai;
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begin
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p := BlockStart;
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while (p <> BlockEnd) Do
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begin
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case p.Typ Of
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Ait_Instruction:
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begin
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if InsContainsSegRef(taicpu(p)) then
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begin
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p := tai(p.next);
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continue;
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end;
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case taicpu(p).opcode Of
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A_IMUL:
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if PrePeepholeOptIMUL(p) then
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Continue;
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A_SAR,A_SHR:
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if PrePeepholeOptSxx(p) then
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continue;
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A_XOR:
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if (taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[0]^.reg = taicpu(p).oper[1]^.reg) then
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{ temporarily change this to 'mov reg,0' to make it easier }
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{ for the CSE. Will be changed back in pass 2 }
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begin
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taicpu(p).opcode := A_MOV;
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taicpu(p).loadConst(0,0);
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end;
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end;
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end;
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end;
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p := tai(p.next)
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end;
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end;
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{ First pass of peephole optimizations }
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procedure TCPUAsmOPtimizer.PeepHoleOptPass1;
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function WriteOk : Boolean;
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begin
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writeln('Ok');
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Result:=True;
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end;
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var
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l : longint;
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p,hp1,hp2 : tai;
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hp3,hp4: tai;
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v:aint;
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function GetFinalDestination(asml: TAsmList; hp: taicpu; level: longint): boolean;
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{traces sucessive jumps to their final destination and sets it, e.g.
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je l1 je l3
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<code> <code>
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l1: becomes l1:
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je l2 je l3
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<code> <code>
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l2: l2:
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jmp l3 jmp l3
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the level parameter denotes how deeep we have already followed the jump,
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to avoid endless loops with constructs such as "l5: ; jmp l5" }
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var p1, p2: tai;
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l: tasmlabel;
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function FindAnyLabel(hp: tai; var l: tasmlabel): Boolean;
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begin
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FindAnyLabel := false;
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while assigned(hp.next) and
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(tai(hp.next).typ in (SkipInstr+[ait_align])) Do
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hp := tai(hp.next);
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if assigned(hp.next) and
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(tai(hp.next).typ = ait_label) then
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begin
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FindAnyLabel := true;
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l := tai_label(hp.next).labsym;
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end
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end;
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begin
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GetfinalDestination := false;
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if level > 20 then
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exit;
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p1 := getlabelwithsym(tasmlabel(hp.oper[0]^.ref^.symbol));
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if assigned(p1) then
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begin
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SkipLabels(p1,p1);
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if (tai(p1).typ = ait_instruction) and
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(taicpu(p1).is_jmp) then
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if { the next instruction after the label where the jump hp arrives}
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{ is unconditional or of the same type as hp, so continue }
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(taicpu(p1).condition in [C_None,hp.condition]) or
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{ the next instruction after the label where the jump hp arrives}
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{ is the opposite of hp (so this one is never taken), but after }
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{ that one there is a branch that will be taken, so perform a }
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{ little hack: set p1 equal to this instruction (that's what the}
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{ last SkipLabels is for, only works with short bool evaluation)}
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((taicpu(p1).condition = inverse_cond(hp.condition)) and
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SkipLabels(p1,p2) and
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(p2.typ = ait_instruction) and
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(taicpu(p2).is_jmp) and
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(taicpu(p2).condition in [C_None,hp.condition]) and
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SkipLabels(p1,p1)) then
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begin
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{ quick check for loops of the form "l5: ; jmp l5 }
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if (tasmlabel(taicpu(p1).oper[0]^.ref^.symbol).labelnr =
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tasmlabel(hp.oper[0]^.ref^.symbol).labelnr) then
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exit;
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if not GetFinalDestination(asml, taicpu(p1),succ(level)) then
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exit;
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tasmlabel(hp.oper[0]^.ref^.symbol).decrefs;
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hp.oper[0]^.ref^.symbol:=taicpu(p1).oper[0]^.ref^.symbol;
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tasmlabel(hp.oper[0]^.ref^.symbol).increfs;
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end
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else
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if (taicpu(p1).condition = inverse_cond(hp.condition)) then
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if not FindAnyLabel(p1,l) then
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begin
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{$ifdef finaldestdebug}
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insertllitem(asml,p1,p1.next,tai_comment.Create(
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strpnew('previous label inserted'))));
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{$endif finaldestdebug}
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current_asmdata.getjumplabel(l);
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insertllitem(p1,p1.next,tai_label.Create(l));
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tasmlabel(taicpu(hp).oper[0]^.ref^.symbol).decrefs;
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hp.oper[0]^.ref^.symbol := l;
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l.increfs;
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{ this won't work, since the new label isn't in the labeltable }
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{ so it will fail the rangecheck. Labeltable should become a }
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{ hashtable to support this: }
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{ GetFinalDestination(asml, hp); }
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end
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else
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begin
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{$ifdef finaldestdebug}
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insertllitem(asml,p1,p1.next,tai_comment.Create(
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strpnew('next label reused'))));
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{$endif finaldestdebug}
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l.increfs;
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hp.oper[0]^.ref^.symbol := l;
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if not GetFinalDestination(asml, hp,succ(level)) then
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exit;
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end;
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end;
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GetFinalDestination := true;
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end;
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begin
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p := BlockStart;
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ClearUsedRegs;
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while (p <> BlockEnd) Do
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begin
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UpDateUsedRegs(UsedRegs, tai(p.next));
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case p.Typ Of
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ait_instruction:
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begin
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current_filepos:=taicpu(p).fileinfo;
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if InsContainsSegRef(taicpu(p)) then
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begin
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p := tai(p.next);
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continue;
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end;
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{ Handle Jmp Optimizations }
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if taicpu(p).is_jmp then
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begin
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{ the following if-block removes all code between a jmp and the next label,
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because it can never be executed }
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if (taicpu(p).opcode = A_JMP) then
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begin
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hp2:=p;
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while GetNextInstruction(hp2, hp1) and
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(hp1.typ <> ait_label) do
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if not(hp1.typ in ([ait_label]+skipinstr)) then
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begin
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{ don't kill start/end of assembler block,
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no-line-info-start/end etc }
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if not(hp1.typ in [ait_align,ait_marker]) then
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begin
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asml.remove(hp1);
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hp1.free;
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end
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else
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hp2:=hp1;
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end
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else break;
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end;
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{ remove jumps to a label coming right after them }
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if GetNextInstruction(p, hp1) then
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begin
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if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol), hp1) and
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{ TODO: FIXME removing the first instruction fails}
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(p<>blockstart) then
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begin
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hp2:=tai(hp1.next);
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asml.remove(p);
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p.free;
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p:=hp2;
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continue;
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end
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else
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begin
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if hp1.typ = ait_label then
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SkipLabels(hp1,hp1);
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if (tai(hp1).typ=ait_instruction) and
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(taicpu(hp1).opcode=A_JMP) and
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GetNextInstruction(hp1, hp2) and
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FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol), hp2) then
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begin
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if taicpu(p).opcode=A_Jcc then
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begin
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taicpu(p).condition:=inverse_cond(taicpu(p).condition);
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tai_label(hp2).labsym.decrefs;
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taicpu(p).oper[0]^.ref^.symbol:=taicpu(hp1).oper[0]^.ref^.symbol;
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{ when free'ing hp1, the ref. isn't decresed, so we don't
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increase it (FK)
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taicpu(p).oper[0]^.ref^.symbol.increfs;
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}
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asml.remove(hp1);
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hp1.free;
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GetFinalDestination(asml, taicpu(p),0);
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end
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else
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begin
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GetFinalDestination(asml, taicpu(p),0);
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p:=tai(p.next);
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continue;
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end;
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end
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else
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GetFinalDestination(asml, taicpu(p),0);
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end;
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end;
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end
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else
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{ All other optimizes }
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begin
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case taicpu(p).opcode Of
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A_AND:
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if OptPass1And(p) then
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continue;
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A_CMP:
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begin
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{ cmp register,$8000 neg register
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je target --> jo target
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.... only if register is deallocated before jump.}
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case Taicpu(p).opsize of
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S_B: v:=$80;
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S_W: v:=$8000;
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S_L: v:=aint($80000000);
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else
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internalerror(2013112905);
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end;
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if (taicpu(p).oper[0]^.typ=Top_const) and
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(taicpu(p).oper[0]^.val=v) and
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(Taicpu(p).oper[1]^.typ=top_reg) and
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GetNextInstruction(p, hp1) and
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(hp1.typ=ait_instruction) and
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(taicpu(hp1).opcode=A_Jcc) and
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(Taicpu(hp1).condition in [C_E,C_NE]) and
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not(RegInUsedRegs(Taicpu(p).oper[1]^.reg, UsedRegs)) then
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begin
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Taicpu(p).opcode:=A_NEG;
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Taicpu(p).loadoper(0,Taicpu(p).oper[1]^);
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Taicpu(p).clearop(1);
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Taicpu(p).ops:=1;
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if Taicpu(hp1).condition=C_E then
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Taicpu(hp1).condition:=C_O
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else
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Taicpu(hp1).condition:=C_NO;
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continue;
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end;
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{
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@@2: @@2:
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.... ....
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cmp operand1,0
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jle/jbe @@1
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dec operand1 --> sub operand1,1
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jmp @@2 jge/jae @@2
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@@1: @@1:
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... ....}
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if (taicpu(p).oper[0]^.typ = top_const) and
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(taicpu(p).oper[1]^.typ in [top_reg,top_ref]) and
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(taicpu(p).oper[0]^.val = 0) and
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GetNextInstruction(p, hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).is_jmp) and
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(taicpu(hp1).opcode=A_Jcc) and
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(taicpu(hp1).condition in [C_LE,C_BE]) and
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GetNextInstruction(hp1,hp2) and
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(hp2.typ = ait_instruction) and
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(taicpu(hp2).opcode = A_DEC) and
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OpsEqual(taicpu(hp2).oper[0]^,taicpu(p).oper[1]^) and
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GetNextInstruction(hp2, hp3) and
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(hp3.typ = ait_instruction) and
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(taicpu(hp3).is_jmp) and
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(taicpu(hp3).opcode = A_JMP) and
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GetNextInstruction(hp3, hp4) and
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FindLabel(tasmlabel(taicpu(hp1).oper[0]^.ref^.symbol),hp4) then
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begin
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taicpu(hp2).Opcode := A_SUB;
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taicpu(hp2).loadoper(1,taicpu(hp2).oper[0]^);
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taicpu(hp2).loadConst(0,1);
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taicpu(hp2).ops:=2;
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taicpu(hp3).Opcode := A_Jcc;
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case taicpu(hp1).condition of
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C_LE: taicpu(hp3).condition := C_GE;
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C_BE: taicpu(hp3).condition := C_AE;
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end;
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asml.remove(p);
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asml.remove(hp1);
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p.free;
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hp1.free;
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p := hp2;
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continue;
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end
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end;
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A_FLD:
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if OptPass1FLD(p) then
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continue;
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A_FSTP,A_FISTP:
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if OptPass1FSTP(p) then
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continue;
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A_LEA:
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begin
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if OptPass1LEA(p) then
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continue;
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end;
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A_MOV:
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begin
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If OptPass1MOV(p) then
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Continue;
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end;
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A_MOVSX,
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A_MOVZX :
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begin
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If OptPass1Movx(p) then
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Continue
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end;
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(* should not be generated anymore by the current code generator
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A_POP:
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begin
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if target_info.system=system_i386_go32v2 then
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begin
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{ Transform a series of pop/pop/pop/push/push/push to }
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{ 'movl x(%esp),%reg' for go32v2 (not for the rest, }
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{ because I'm not sure whether they can cope with }
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{ 'movl x(%esp),%reg' with x > 0, I believe we had }
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{ such a problem when using esp as frame pointer (JM) }
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if (taicpu(p).oper[0]^.typ = top_reg) then
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begin
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hp1 := p;
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hp2 := p;
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l := 0;
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while getNextInstruction(hp1,hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).opcode = A_POP) and
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(taicpu(hp1).oper[0]^.typ = top_reg) do
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begin
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hp2 := hp1;
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inc(l,4);
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end;
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getLastInstruction(p,hp3);
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l1 := 0;
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while (hp2 <> hp3) and
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assigned(hp1) and
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(hp1.typ = ait_instruction) and
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(taicpu(hp1).opcode = A_PUSH) and
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(taicpu(hp1).oper[0]^.typ = top_reg) and
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(taicpu(hp1).oper[0]^.reg.enum = taicpu(hp2).oper[0]^.reg.enum) do
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begin
|
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{ change it to a two op operation }
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taicpu(hp2).oper[1]^.typ:=top_none;
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taicpu(hp2).ops:=2;
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taicpu(hp2).opcode := A_MOV;
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taicpu(hp2).loadoper(1,taicpu(hp1).oper[0]^);
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reference_reset(tmpref);
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tmpRef.base.enum:=R_INTREGISTER;
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tmpRef.base.number:=NR_STACK_POINTER_REG;
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convert_register_to_enum(tmpref.base);
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tmpRef.offset := l;
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taicpu(hp2).loadRef(0,tmpRef);
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hp4 := hp1;
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getNextInstruction(hp1,hp1);
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asml.remove(hp4);
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hp4.free;
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getLastInstruction(hp2,hp2);
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dec(l,4);
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inc(l1);
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end;
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if l <> -4 then
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begin
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inc(l,4);
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for l1 := l1 downto 1 do
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begin
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getNextInstruction(hp2,hp2);
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dec(taicpu(hp2).oper[0]^.ref^.offset,l);
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end
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end
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end
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end
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else
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begin
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if (taicpu(p).oper[0]^.typ = top_reg) and
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GetNextInstruction(p, hp1) and
|
|
(tai(hp1).typ=ait_instruction) and
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|
(taicpu(hp1).opcode=A_PUSH) and
|
|
(taicpu(hp1).oper[0]^.typ = top_reg) and
|
|
(taicpu(hp1).oper[0]^.reg.enum=taicpu(p).oper[0]^.reg.enum) then
|
|
begin
|
|
{ change it to a two op operation }
|
|
taicpu(p).oper[1]^.typ:=top_none;
|
|
taicpu(p).ops:=2;
|
|
taicpu(p).opcode := A_MOV;
|
|
taicpu(p).loadoper(1,taicpu(p).oper[0]^);
|
|
reference_reset(tmpref);
|
|
TmpRef.base.enum := R_ESP;
|
|
taicpu(p).loadRef(0,TmpRef);
|
|
asml.remove(hp1);
|
|
hp1.free;
|
|
end;
|
|
end;
|
|
end;
|
|
*)
|
|
A_PUSH:
|
|
begin
|
|
if (taicpu(p).opsize = S_W) and
|
|
(taicpu(p).oper[0]^.typ = Top_Const) and
|
|
GetNextInstruction(p, hp1) and
|
|
(tai(hp1).typ = ait_instruction) and
|
|
(taicpu(hp1).opcode = A_PUSH) and
|
|
(taicpu(hp1).oper[0]^.typ = Top_Const) and
|
|
(taicpu(hp1).opsize = S_W) then
|
|
begin
|
|
taicpu(p).changeopsize(S_L);
|
|
taicpu(p).loadConst(0,taicpu(p).oper[0]^.val shl 16 + word(taicpu(hp1).oper[0]^.val));
|
|
asml.remove(hp1);
|
|
hp1.free;
|
|
end;
|
|
end;
|
|
A_SHL, A_SAL:
|
|
if OptPass1SHLSAL(p) then
|
|
Continue;
|
|
A_SUB:
|
|
if OptPass1Sub(p) then
|
|
continue;
|
|
A_VMOVAPS,
|
|
A_VMOVAPD:
|
|
if OptPass1VMOVAP(p) then
|
|
continue;
|
|
A_VDIVSD,
|
|
A_VDIVSS,
|
|
A_VSUBSD,
|
|
A_VSUBSS,
|
|
A_VMULSD,
|
|
A_VMULSS,
|
|
A_VADDSD,
|
|
A_VADDSS,
|
|
A_VANDPD,
|
|
A_VANDPS,
|
|
A_VORPD,
|
|
A_VORPS,
|
|
A_VXORPD,
|
|
A_VXORPS:
|
|
if OptPass1VOP(p) then
|
|
continue;
|
|
A_MULSD,
|
|
A_MULSS,
|
|
A_ADDSD,
|
|
A_ADDSS:
|
|
if OptPass1OP(p) then
|
|
continue;
|
|
A_MOVAPD,
|
|
A_MOVAPS:
|
|
if OptPass1MOVAP(p) then
|
|
continue;
|
|
A_VMOVSD,
|
|
A_VMOVSS,
|
|
A_MOVSD,
|
|
A_MOVSS:
|
|
if OptPass1MOVXX(p) then
|
|
continue;
|
|
A_SETcc:
|
|
if OptPass1SETcc(p) then
|
|
continue;
|
|
end;
|
|
end; { if is_jmp }
|
|
end;
|
|
end;
|
|
updateUsedRegs(UsedRegs,p);
|
|
p:=tai(p.next);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure TCPUAsmOptimizer.PeepHoleOptPass2;
|
|
var
|
|
p : tai;
|
|
begin
|
|
p := BlockStart;
|
|
ClearUsedRegs;
|
|
while (p <> BlockEnd) Do
|
|
begin
|
|
UpdateUsedRegs(UsedRegs, tai(p.next));
|
|
case p.Typ Of
|
|
Ait_Instruction:
|
|
begin
|
|
if InsContainsSegRef(taicpu(p)) then
|
|
begin
|
|
p := tai(p.next);
|
|
continue;
|
|
end;
|
|
case taicpu(p).opcode Of
|
|
A_Jcc:
|
|
if OptPass2Jcc(p) then
|
|
continue;
|
|
A_FSTP,A_FISTP:
|
|
if OptPass1FSTP(p) then
|
|
continue;
|
|
A_IMUL:
|
|
if OptPass2Imul(p) then
|
|
continue;
|
|
A_JMP:
|
|
if OptPass2Jmp(p) then
|
|
continue;
|
|
A_MOV:
|
|
if OptPass2MOV(p) then
|
|
continue;
|
|
end;
|
|
end;
|
|
end;
|
|
p := tai(p.next)
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure TCPUAsmOptimizer.PostPeepHoleOpts;
|
|
var
|
|
p,hp1: tai;
|
|
begin
|
|
p := BlockStart;
|
|
ClearUsedRegs;
|
|
while (p <> BlockEnd) Do
|
|
begin
|
|
UpdateUsedRegs(UsedRegs, tai(p.next));
|
|
case p.Typ Of
|
|
Ait_Instruction:
|
|
begin
|
|
if InsContainsSegRef(taicpu(p)) then
|
|
begin
|
|
p := tai(p.next);
|
|
continue;
|
|
end;
|
|
case taicpu(p).opcode Of
|
|
A_CALL:
|
|
if PostPeepHoleOptCall(p) then
|
|
Continue;
|
|
A_LEA:
|
|
if PostPeepholeOptLea(p) then
|
|
Continue;
|
|
A_CMP:
|
|
if PostPeepholeOptCmp(p) then
|
|
Continue;
|
|
A_MOV:
|
|
if PostPeepholeOptMov(p) then
|
|
Continue;
|
|
A_MOVZX:
|
|
{ if register vars are on, it's possible there is code like }
|
|
{ "cmpl $3,%eax; movzbl 8(%ebp),%ebx; je .Lxxx" }
|
|
{ so we can't safely replace the movzx then with xor/mov, }
|
|
{ since that would change the flags (JM) }
|
|
if not(cs_opt_regvar in current_settings.optimizerswitches) then
|
|
begin
|
|
if (taicpu(p).oper[1]^.typ = top_reg) then
|
|
if (taicpu(p).oper[0]^.typ = top_reg)
|
|
then
|
|
case taicpu(p).opsize of
|
|
S_BL:
|
|
begin
|
|
if IsGP32Reg(taicpu(p).oper[1]^.reg) and
|
|
not(cs_opt_size in current_settings.optimizerswitches) and
|
|
(current_settings.optimizecputype = cpu_Pentium) then
|
|
{Change "movzbl %reg1, %reg2" to
|
|
"xorl %reg2, %reg2; movb %reg1, %reg2" for Pentium and
|
|
PentiumMMX}
|
|
begin
|
|
hp1 := taicpu.op_reg_reg(A_XOR, S_L,
|
|
taicpu(p).oper[1]^.reg, taicpu(p).oper[1]^.reg);
|
|
InsertLLItem(p.previous, p, hp1);
|
|
taicpu(p).opcode := A_MOV;
|
|
taicpu(p).changeopsize(S_B);
|
|
setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
|
|
end;
|
|
end;
|
|
end
|
|
else if (taicpu(p).oper[0]^.typ = top_ref) and
|
|
(taicpu(p).oper[0]^.ref^.base <> taicpu(p).oper[1]^.reg) and
|
|
(taicpu(p).oper[0]^.ref^.index <> taicpu(p).oper[1]^.reg) and
|
|
not(cs_opt_size in current_settings.optimizerswitches) and
|
|
IsGP32Reg(taicpu(p).oper[1]^.reg) and
|
|
(current_settings.optimizecputype = cpu_Pentium) and
|
|
(taicpu(p).opsize = S_BL) then
|
|
{changes "movzbl mem, %reg" to "xorl %reg, %reg; movb mem, %reg8" for
|
|
Pentium and PentiumMMX}
|
|
begin
|
|
hp1 := taicpu.Op_reg_reg(A_XOR, S_L, taicpu(p).oper[1]^.reg,
|
|
taicpu(p).oper[1]^.reg);
|
|
taicpu(p).opcode := A_MOV;
|
|
taicpu(p).changeopsize(S_B);
|
|
setsubreg(taicpu(p).oper[1]^.reg,R_SUBL);
|
|
InsertLLItem(p.previous, p, hp1);
|
|
end;
|
|
end;
|
|
A_TEST, A_OR:
|
|
if PostPeepholeOptTestOr(p) then
|
|
Continue;
|
|
end;
|
|
end;
|
|
end;
|
|
p := tai(p.next)
|
|
end;
|
|
OptReferences;
|
|
end;
|
|
|
|
|
|
Procedure TCpuAsmOptimizer.Optimize;
|
|
Var
|
|
HP: Tai;
|
|
pass: longint;
|
|
slowopt, changed, lastLoop: boolean;
|
|
Begin
|
|
slowopt := (cs_opt_level3 in current_settings.optimizerswitches);
|
|
pass := 0;
|
|
changed := false;
|
|
repeat
|
|
lastLoop :=
|
|
not(slowopt) or
|
|
(not changed and (pass > 2)) or
|
|
{ prevent endless loops }
|
|
(pass = 4);
|
|
changed := false;
|
|
{ Setup labeltable, always necessary }
|
|
blockstart := tai(asml.first);
|
|
pass_1;
|
|
{ Blockend now either contains an ait_marker with Kind = mark_AsmBlockStart, }
|
|
{ or nil }
|
|
While Assigned(BlockStart) Do
|
|
Begin
|
|
if (cs_opt_peephole in current_settings.optimizerswitches) then
|
|
begin
|
|
if (pass = 0) then
|
|
PrePeepHoleOpts;
|
|
{ Peephole optimizations }
|
|
PeepHoleOptPass1;
|
|
{ Only perform them twice in the first pass }
|
|
if pass = 0 then
|
|
PeepHoleOptPass1;
|
|
end;
|
|
{ More peephole optimizations }
|
|
if (cs_opt_peephole in current_settings.optimizerswitches) then
|
|
begin
|
|
PeepHoleOptPass2;
|
|
if lastLoop then
|
|
PostPeepHoleOpts;
|
|
end;
|
|
|
|
{ Continue where we left off, BlockEnd is either the start of an }
|
|
{ assembler block or nil }
|
|
BlockStart := BlockEnd;
|
|
While Assigned(BlockStart) And
|
|
(BlockStart.typ = ait_Marker) And
|
|
(Tai_Marker(BlockStart).Kind = mark_AsmBlockStart) Do
|
|
Begin
|
|
{ We stopped at an assembler block, so skip it }
|
|
Repeat
|
|
BlockStart := Tai(BlockStart.Next);
|
|
Until (BlockStart.Typ = Ait_Marker) And
|
|
(Tai_Marker(Blockstart).Kind = mark_AsmBlockEnd);
|
|
{ Blockstart now contains a Tai_marker(mark_AsmBlockEnd) }
|
|
If GetNextInstruction(BlockStart, HP) And
|
|
((HP.typ <> ait_Marker) Or
|
|
(Tai_Marker(HP).Kind <> mark_AsmBlockStart)) Then
|
|
{ There is no assembler block anymore after the current one, so }
|
|
{ optimize the next block of "normal" instructions }
|
|
pass_1
|
|
{ Otherwise, skip the next assembler block }
|
|
else
|
|
blockStart := hp;
|
|
End;
|
|
End;
|
|
inc(pass);
|
|
until lastLoop;
|
|
dfa.free;
|
|
|
|
End;
|
|
|
|
|
|
begin
|
|
casmoptimizer:=TCpuAsmOptimizer;
|
|
end.
|
|
|