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a64att.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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a64atts.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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a64ins.dat
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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a64nop.inc
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a64op.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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a64reg.dat
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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a64tab.inc
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aasmcpu.pas
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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agcpugas.pas
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Add explicit longint typecast to avoid range check errors with unwindrec longword variable
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2020-10-28 09:46:02 +00:00 |
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aoptcpu.pas
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Move explicit typecast to after check to avoid RTE when compiled with -CR
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2020-11-09 21:19:40 +00:00 |
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aoptcpub.pas
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* fix case completeness and unreachable code warnings in compiler that would
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2019-05-12 14:29:03 +00:00 |
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aoptcpud.pas
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cgcpu.pas
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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cpubase.pas
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+ Add new LastCommonAsmOp constant to arm and aarch64 CPU targets.
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2020-10-19 09:19:25 +00:00 |
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cpuinfo.pas
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* disable cs_opt_regvar on all platforms when compiled for LLVM (LLVM does
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2020-01-29 22:21:07 +00:00 |
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cpunode.pas
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+ implement compiler support for SEH on Win64
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2020-04-21 06:06:05 +00:00 |
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cpupara.pas
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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cpupi.pas
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+ implement compiler support for SEH on Win64
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2020-04-21 06:06:05 +00:00 |
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cputarg.pas
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+ implement initial compiler support for Win64 on Aarch64
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2020-04-21 06:04:22 +00:00 |
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hlcgcpu.pas
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* patch by Marģers to unify internal error numbers, resolves #37888
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2020-10-13 19:59:01 +00:00 |
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itcpugas.pas
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ncpuadd.pas
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+ support for software floating point exception handling on AArch64 (-CE)
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2019-09-01 17:26:11 +00:00 |
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ncpucnv.pas
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* Removed unused local vars.
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2018-11-02 18:44:29 +00:00 |
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ncpucon.pas
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* avoid that -0.0 is handled by the eor optimization
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2019-09-04 20:45:24 +00:00 |
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ncpuflw.pas
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* patch by Marģers to unify internal error numbers, resolves #37888
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2020-10-13 19:59:01 +00:00 |
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ncpuinl.pas
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+ support for software floating point exception handling on AArch64 (-CE)
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2019-09-01 17:26:11 +00:00 |
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ncpumat.pas
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* reworked usage of tcgnotnode.handle_locjump
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2020-08-05 21:15:32 +00:00 |
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ncpumem.pas
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ncpuset.pas
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* generate jump tables into the same section as the code as otherwise we'll get bogus relocations (in case of clang.exe) or a future support for armasm64.exe will reject the relative symbols outright
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2020-04-21 06:06:36 +00:00 |
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ra64con.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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ra64dwa.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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ra64nor.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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ra64num.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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ra64rni.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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ra64sri.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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ra64sta.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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ra64std.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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ra64sup.inc
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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racpu.pas
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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racpugas.pas
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* AArch64: added SIMD instructions (only plain ARMv8-A for now)
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2020-10-15 20:29:36 +00:00 |
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rgcpu.pas
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+ Aarch64: trgcpu.get_spill_subreg: return MM sub register correctly, resolves #37393
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2020-07-20 21:07:09 +00:00 |
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symcpu.pas
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tripletcpu.pas
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* mark all external assemblers using an LLVM tool using af_llvm
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2020-07-19 14:30:35 +00:00 |
