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ec04a5a899
third operand can only be a const or register CL, so it doesn't
affect spilling
* support shrd/shld that don't allow memory operands
644 lines
26 KiB
ObjectPascal
644 lines
26 KiB
ObjectPascal
{
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$Id$
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit implements the x86 specific class for the register
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allocator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit rgx86;
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{$i fpcdefs.inc}
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interface
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uses
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cpubase,
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cpuinfo,
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aasmbase,aasmtai,aasmcpu,
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cclasses,globtype,cgbase,rgobj;
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type
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trgx86 = class(trgobj)
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function instr_spill_register(list:Taasmoutput;
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instr:taicpu;
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const r:Tsuperregisterset;
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const spilltemplist:Tspill_temp_list): boolean;override;
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end;
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tpushedsavedloc = record
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case byte of
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0: (pushed: boolean);
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1: (ofs: longint);
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end;
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tpushedsavedfpu = array[tsuperregister] of tpushedsavedloc;
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trgx86fpu = class
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{ The "usableregsxxx" contain all registers of type "xxx" that }
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{ aren't currently allocated to a regvar. The "unusedregsxxx" }
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{ contain all registers of type "xxx" that aren't currently }
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{ allocated }
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unusedregsfpu,usableregsfpu : Tsuperregisterset;
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{ these counters contain the number of elements in the }
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{ unusedregsxxx/usableregsxxx sets }
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countunusedregsfpu : byte;
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{ Contains the registers which are really used by the proc itself.
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It doesn't take care of registers used by called procedures
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}
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used_in_proc : tcpuregisterset;
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{reg_pushes_other : regvarother_longintarray;
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is_reg_var_other : regvarother_booleanarray;
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regvar_loaded_other : regvarother_booleanarray;}
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{ tries to hold the amount of times which the current tree is processed }
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t_times: longint;
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fpuvaroffset : byte;
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constructor create;
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function getregisterfpu(list: taasmoutput) : tregister;
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procedure ungetregisterfpu(list: taasmoutput; r : tregister);
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{ pushes and restores registers }
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procedure saveusedfpuregisters(list:Taasmoutput;
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var saved:Tpushedsavedfpu;
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const s:Tcpuregisterset);
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procedure restoreusedfpuregisters(list:Taasmoutput;
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const saved:Tpushedsavedfpu);
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{ corrects the fpu stack register by ofs }
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function correct_fpuregister(r : tregister;ofs : byte) : tregister;
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end;
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implementation
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uses
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systems,
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verbose;
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const
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{ This value is used in tsaved. If the array value is equal
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to this, then this means that this register is not used.}
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reg_not_saved = $7fffffff;
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{******************************************************************************
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Trgcpu
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******************************************************************************}
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function trgx86.instr_spill_register(list:Taasmoutput;
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instr:taicpu;
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const r:Tsuperregisterset;
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const spilltemplist:Tspill_temp_list): boolean;
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{
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Spill the registers in r in this instruction. Returns true if any help
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registers are used. This procedure has become one big hack party, because
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of the huge amount of situations you can have. The irregularity of the i386
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instruction set doesn't help either. (DM)
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}
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var i:byte;
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supreg:Tsuperregister;
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subreg:Tsubregister;
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helpreg:Tregister;
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helpins:Taicpu;
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op:Tasmop;
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hopsize:Topsize;
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pos:Tai;
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begin
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{Situation examples are in intel notation, so operand order:
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mov eax , ebx
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^^^ ^^^
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oper[1] oper[0]
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(DM)}
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result:=false;
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with taicpu(instr) do
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begin
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case ops of
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0:
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;
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1:
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begin
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if (oper[0]^.typ=top_reg) and
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(getregtype(oper[0]^.reg)=regtype) then
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begin
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supreg:=getsupreg(oper[0]^.reg);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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push r20d ; r20d must be spilled into [ebp-12]
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Change into:
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push [ebp-12] ; Replace register by reference }
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{ hopsize:=reg2opsize(oper[0].reg);}
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oper[0]^.typ:=top_ref;
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new(oper[0]^.ref);
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oper[0]^.ref^:=spilltemplist[supreg];
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{ oper[0]^.ref^.size:=hopsize;}
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end;
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end;
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if oper[0]^.typ=top_ref then
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begin
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supreg:=getsupreg(oper[0]^.ref^.base);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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push [r21d+4*r22d] ; r21d must be spilled into [ebp-12]
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Change into:
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mov r23d,[ebp-12] ; Use a help register
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push [r23d+4*r22d] ; Replace register by helpregister }
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subreg:=getsubreg(oper[0]^.ref^.base);
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if oper[0]^.ref^.index=NR_NO then
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pos:=Tai(previous)
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else
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pos:=get_insert_pos(Tai(previous),getsupreg(oper[0]^.ref^.index),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[0]^.ref^.base),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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oper[0]^.ref^.base:=helpreg;
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end;
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supreg:=getsupreg(oper[0]^.ref^.index);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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push [r21d+4*r22d] ; r22d must be spilled into [ebp-12]
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Change into:
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mov r23d,[ebp-12] ; Use a help register
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push [r21d+4*r23d] ; Replace register by helpregister }
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subreg:=getsubreg(oper[0]^.ref^.index);
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if oper[0]^.ref^.base=NR_NO then
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pos:=Tai(instr.previous)
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else
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[0]^.ref^.base),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[0]^.ref^.index),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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oper[0]^.ref^.index:=helpreg;
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end;
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end;
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end;
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2,
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3 :
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begin
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{ Opcodes with 3 registers are shrd/shld, where the 3rd operand is const or CL,
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that doesn't need spilling }
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{ First spill the registers from the references. This is
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required because the reference can be moved from this instruction
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to a MOV instruction when spilling of the register operand is done }
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for i:=0 to 1 do
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if oper[i]^.typ=top_ref then
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begin
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supreg:=getsupreg(oper[i]^.ref^.base);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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add r20d,[r21d+4*r22d] ; r21d must be spilled into [ebp-12]
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Change into:
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mov r23d,[ebp-12] ; Use a help register
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add r20d,[r23d+4*r22d] ; Replace register by helpregister }
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subreg:=getsubreg(oper[i]^.ref^.base);
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if i=1 then
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[i]^.ref^.index),getsupreg(oper[0]^.reg),RS_INVALID)
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else
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[i]^.ref^.index),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[i]^.ref^.base),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[i]^.ref^.base:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end;
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supreg:=getsupreg(oper[i]^.ref^.index);
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if supregset_in(r,supreg) then
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begin
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{Situation example:
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add r20d,[r21d+4*r22d] ; r22d must be spilled into [ebp-12]
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Change into:
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mov r23d,[ebp-12] ; Use a help register
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add r20d,[r21d+4*r23d] ; Replace register by helpregister }
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subreg:=getsubreg(oper[i]^.ref^.index);
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if i=1 then
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[i]^.ref^.base),
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getsupreg(oper[0]^.reg),RS_INVALID)
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else
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[i]^.ref^.base),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[i]^.ref^.index),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[i]^.ref^.index:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end;
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end;
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if (oper[0]^.typ=top_reg) and
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(getregtype(oper[0]^.reg)=regtype) then
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begin
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supreg:=getsupreg(oper[0]^.reg);
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subreg:=getsubreg(oper[0]^.reg);
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if supregset_in(r,supreg) then
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if oper[1]^.typ=top_ref then
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begin
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{Situation example:
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add [r20d],r21d ; r21d must be spilled into [ebp-12]
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Change into:
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mov r22d,[ebp-12] ; Use a help register
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add [r20d],r22d ; Replace register by helpregister }
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[0]^.reg),
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getsupreg(oper[1]^.ref^.base),getsupreg(oper[1]^.ref^.index));
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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helpins:=Taicpu.op_ref_reg(A_MOV,reg2opsize(oper[0]^.reg),spilltemplist[supreg],helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[0]^.reg:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end
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else
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begin
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{Situation example:
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add r20d,r21d ; r21d must be spilled into [ebp-12]
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Change into:
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add r20d,[ebp-12] ; Replace register by reference }
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oper[0]^.typ:=top_ref;
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new(oper[0]^.ref);
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oper[0]^.ref^:=spilltemplist[supreg];
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end;
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end;
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if (oper[1]^.typ=top_reg) and
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(getregtype(oper[1]^.reg)=regtype) then
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begin
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supreg:=getsupreg(oper[1]^.reg);
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subreg:=getsubreg(oper[1]^.reg);
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if supregset_in(r,supreg) then
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begin
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if oper[0]^.typ=top_ref then
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begin
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{Situation example:
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add r20d,[r21d] ; r20d must be spilled into [ebp-12]
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Change into:
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mov r22d,[r21d] ; Use a help register
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add [ebp-12],r22d ; Replace register by helpregister }
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[0]^.ref^.base),
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getsupreg(oper[0]^.ref^.index),RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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result:=true;
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op:=A_MOV;
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hopsize:=opsize; {Save old value...}
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if (opcode=A_MOVZX) or (opcode=A_MOVSX) or (opcode=A_LEA) then
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begin
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{Because 'movzx memory,register' does not exist...}
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op:=opcode;
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opcode:=A_MOV;
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opsize:=reg2opsize(oper[1]^.reg);
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end;
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helpins:=Taicpu.op_ref_reg(op,hopsize,oper[0]^.ref^,helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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dispose(oper[0]^.ref);
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oper[0]^.typ:=top_reg;
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oper[0]^.reg:=helpreg;
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oper[1]^.typ:=top_ref;
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new(oper[1]^.ref);
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oper[1]^.ref^:=spilltemplist[supreg];
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end
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else
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begin
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{Situation example:
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add r20d,r21d ; r20d must be spilled into [ebp-12]
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Change into:
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add [ebp-12],r21d ; Replace register by reference }
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if (opcode=A_MOVZX) or (opcode=A_MOVSX) then
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begin
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{Because 'movzx memory,register' does not exist...}
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result:=true;
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op:=opcode;
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hopsize:=opsize;
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opcode:=A_MOV;
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opsize:=reg2opsize(oper[1]^.reg);
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pos:=get_insert_pos(Tai(instr.previous),getsupreg(oper[0]^.reg),RS_INVALID,RS_INVALID);
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getregisterinline(list,pos,subreg,helpreg);
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helpins:=Taicpu.op_reg_reg(op,hopsize,oper[0]^.reg,helpreg);
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if pos=nil then
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list.insertafter(helpins,list.first)
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else
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list.insertafter(helpins,pos.next);
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oper[0]^.reg:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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forward_allocation(Tai(helpins.next),instr);
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end;
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oper[1]^.typ:=top_ref;
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new(oper[1]^.ref);
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oper[1]^.ref^:=spilltemplist[supreg];
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end;
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end;
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end;
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{ The i386 instruction set never gets boring...
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some opcodes do not support a memory location as destination }
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if (oper[1]^.typ=top_ref) and
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(
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(oper[0]^.typ=top_const) or
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((oper[0]^.typ=top_reg) and
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(getregtype(oper[0]^.reg)=regtype))
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) then
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begin
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case opcode of
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A_SHLD,A_SHRD,
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A_IMUL :
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begin
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{Yikes! We just changed the destination register into
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a memory location above here.
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Situation examples:
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imul [ebp-12],r21d ; We need a help register
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imul [ebp-12],<const> ; We need a help register
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Change into:
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mov r22d,[ebp-12] ; Use a help instruction (only for IMUL)
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imul r22d,r21d ; Replace reference by helpregister
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mov [ebp-12],r22d ; Use another help instruction}
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getregisterinline(list,Tai(previous),subreg,helpreg);
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result:=true;
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{First help instruction.}
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helpins:=Taicpu.op_ref_reg(A_MOV,opsize,oper[1]^.ref^,helpreg);
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if previous=nil then
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list.insert(helpins)
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else
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list.insertafter(helpins,previous);
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{Second help instruction.}
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helpins:=Taicpu.op_reg_ref(A_MOV,opsize,helpreg,oper[1]^.ref^);
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dispose(oper[1]^.ref);
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oper[1]^.typ:=top_reg;
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oper[1]^.reg:=helpreg;
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list.insertafter(helpins,instr);
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ungetregisterinline(list,instr,helpreg);
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end;
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end;
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end;
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{ The i386 instruction set never gets boring...
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some opcodes do not support a memory location as source }
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if (oper[0]^.typ=top_ref) and
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(oper[1]^.typ=top_reg) and
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(getregtype(oper[1]^.reg)=regtype) then
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begin
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case opcode of
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A_BT,A_BTS,
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A_BTC,A_BTR :
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begin
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{Yikes! We just changed the source register into
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a memory location above here.
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Situation example:
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bt r21d,[ebp-12] ; We need a help register
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Change into:
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mov r22d,[ebp-12] ; Use a help instruction (only for IMUL)
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bt r21d,r22d ; Replace reference by helpregister}
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getregisterinline(list,Tai(previous),subreg,helpreg);
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result:=true;
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{First help instruction.}
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helpins:=Taicpu.op_ref_reg(A_MOV,opsize,oper[0]^.ref^,helpreg);
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if previous=nil then
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list.insert(helpins)
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else
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list.insertafter(helpins,previous);
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dispose(oper[0]^.ref);
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oper[0]^.typ:=top_reg;
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oper[0]^.reg:=helpreg;
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ungetregisterinline(list,helpins,helpreg);
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end;
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end;
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end;
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end;
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else
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internalerror(200409202);
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end;
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end;
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end;
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{******************************************************************************
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Trgx86fpu
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******************************************************************************}
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constructor Trgx86fpu.create;
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var i:Tsuperregister;
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begin
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used_in_proc:=[];
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t_times := 0;
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unusedregsfpu:=usableregsfpu;
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end;
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function trgx86fpu.getregisterfpu(list: taasmoutput) : tregister;
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begin
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{ note: don't return R_ST0, see comments above implementation of }
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{ a_loadfpu_* methods in cgcpu (JM) }
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result:=NR_ST;
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end;
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procedure trgx86fpu.ungetregisterfpu(list : taasmoutput; r : tregister);
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begin
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{ nothing to do, fpu stack management is handled by the load/ }
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{ store operations in cgcpu (JM) }
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end;
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function trgx86fpu.correct_fpuregister(r : tregister;ofs : byte) : tregister;
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begin
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correct_fpuregister:=r;
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setsupreg(correct_fpuregister,ofs);
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end;
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|
|
|
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procedure trgx86fpu.saveusedfpuregisters(list: taasmoutput;
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var saved : tpushedsavedfpu;
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const s: tcpuregisterset);
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|
var
|
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r : tregister;
|
|
hr : treference;
|
|
begin
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|
used_in_proc:=used_in_proc+s;
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|
|
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{$warning TODO firstsavefpureg}
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|
(*
|
|
{ don't try to save the fpu registers if not desired (e.g. for }
|
|
{ the 80x86) }
|
|
if firstsavefpureg <> R_NO then
|
|
for r.enum:=firstsavefpureg to lastsavefpureg do
|
|
begin
|
|
saved[r.enum].ofs:=reg_not_saved;
|
|
{ if the register is used by the calling subroutine and if }
|
|
{ it's not a regvar (those are handled separately) }
|
|
if not is_reg_var_other[r.enum] and
|
|
(r.enum in s) and
|
|
{ and is present in use }
|
|
not(r.enum in unusedregsfpu) then
|
|
begin
|
|
{ then save it }
|
|
tg.GetTemp(list,extended_size,tt_persistent,hr);
|
|
saved[r.enum].ofs:=hr.offset;
|
|
cg.a_loadfpu_reg_ref(list,OS_FLOAT,r,hr);
|
|
cg.a_reg_dealloc(list,r);
|
|
include(unusedregsfpu,r.enum);
|
|
inc(countunusedregsfpu);
|
|
end;
|
|
end;
|
|
*)
|
|
end;
|
|
|
|
|
|
procedure trgx86fpu.restoreusedfpuregisters(list : taasmoutput;
|
|
const saved : tpushedsavedfpu);
|
|
|
|
var
|
|
r,r2 : tregister;
|
|
hr : treference;
|
|
|
|
begin
|
|
{$warning TODO firstsavefpureg}
|
|
(*
|
|
if firstsavefpureg <> R_NO then
|
|
for r.enum:=lastsavefpureg downto firstsavefpureg do
|
|
begin
|
|
if saved[r.enum].ofs <> reg_not_saved then
|
|
begin
|
|
r2.enum:=R_INTREGISTER;
|
|
r2.number:=NR_FRAME_POINTER_REG;
|
|
reference_reset_base(hr,r2,saved[r.enum].ofs);
|
|
cg.a_reg_alloc(list,r);
|
|
cg.a_loadfpu_ref_reg(list,OS_FLOAT,hr,r);
|
|
if not (r.enum in unusedregsfpu) then
|
|
{ internalerror(10)
|
|
in n386cal we always save/restore the reg *state*
|
|
using save/restoreunusedstate -> the current state
|
|
may not be real (JM) }
|
|
else
|
|
begin
|
|
dec(countunusedregsfpu);
|
|
exclude(unusedregsfpu,r.enum);
|
|
end;
|
|
tg.UnGetTemp(list,hr);
|
|
end;
|
|
end;
|
|
*)
|
|
end;
|
|
|
|
(*
|
|
procedure Trgx86fpu.saveotherregvars(list: taasmoutput; const s: totherregisterset);
|
|
var
|
|
r: Tregister;
|
|
begin
|
|
if not(cs_regvars in aktglobalswitches) then
|
|
exit;
|
|
if firstsavefpureg <> NR_NO then
|
|
for r.enum := firstsavefpureg to lastsavefpureg do
|
|
if is_reg_var_other[r.enum] and
|
|
(r.enum in s) then
|
|
store_regvar(list,r);
|
|
end;
|
|
*)
|
|
|
|
end.
|
|
{
|
|
$Log$
|
|
Revision 1.6 2004-09-27 14:49:45 peter
|
|
* handle 3 operand opcodes the same as 2 operand opcodes, the
|
|
third operand can only be a const or register CL, so it doesn't
|
|
affect spilling
|
|
* support shrd/shld that don't allow memory operands
|
|
|
|
Revision 1.5 2004/09/26 07:15:07 florian
|
|
* ie checking in spilling code improved
|
|
|
|
Revision 1.4 2004/06/20 08:55:32 florian
|
|
* logs truncated
|
|
|
|
Revision 1.3 2004/06/16 20:07:11 florian
|
|
* dwarf branch merged
|
|
|
|
Revision 1.2.2.1 2004/04/10 12:36:42 peter
|
|
* fixed alignment issues
|
|
|
|
Revision 1.2 2004/01/12 16:37:59 peter
|
|
* moved spilling code from taicpu to rg
|
|
|
|
}
|