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https://gitlab.com/freepascal.org/fpc/source.git
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500 lines
22 KiB
ObjectPascal
500 lines
22 KiB
ObjectPascal
{
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Copyright (c) 1998-2002, 2014 by Florian Klaempfl and Jonas Maebe
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Generate AArch64 assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncpumat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat;
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type
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taarch64moddivnode = class(tmoddivnode)
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function pass_1: tnode; override;
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procedure pass_generate_code;override;
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end;
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taarch64notnode = class(tcgnotnode)
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procedure second_boolean;override;
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end;
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taarch64unaryminusnode = class(tcgunaryminusnode)
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procedure second_float; override;
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end;
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implementation
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uses
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globtype,systems,constexp,
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cutils,verbose,globals,
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symconst,symdef,
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aasmbase,aasmcpu,aasmtai,aasmdata,
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defutil,
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cgbase,cgobj,hlcgobj,pass_2,procinfo,
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ncon,
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cpubase,
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ncgutil,cgcpu,cgutils;
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{*****************************************************************************
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taarch64moddivnode
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*****************************************************************************}
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function taarch64moddivnode.pass_1: tnode;
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begin
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result:=inherited pass_1;
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if not assigned(result) then
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include(current_procinfo.flags,pi_do_call);
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end;
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procedure taarch64moddivnode.pass_generate_code;
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var
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op : tasmop;
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tmpreg,
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zeroreg,
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numerator,
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divider,
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largernumreg,
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largerresreg,
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resultreg : tregister;
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hl : tasmlabel;
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overflowloc: tlocation;
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power : longint;
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opsize : tcgsize;
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dividend : Int64;
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high_bit,
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reciprocal : QWord;
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{ Just to save on stack space and the like }
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reciprocal_signed : Int64 absolute reciprocal;
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expandword,
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magic_add : Boolean;
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shift : byte;
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shifterop : tshifterop;
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hp : taicpu;
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procedure genOrdConstNodeDiv;
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var
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helper1, helper2: TRegister;
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so: tshifterop;
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begin
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if tordconstnode(right).value=0 then
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internalerror(2020021601)
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else if tordconstnode(right).value=1 then
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cg.a_load_reg_reg(current_asmdata.CurrAsmList, opsize, opsize, numerator, resultreg)
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else if (tordconstnode(right).value = int64(-1)) then
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begin
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// note: only in the signed case possible..., may overflow
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if cs_check_overflow in current_settings.localswitches then
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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current_asmdata.CurrAsmList.concat(setoppostfix(taicpu.op_reg_reg(A_NEG,
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resultreg,numerator),toppostfix(ord(cs_check_overflow in current_settings.localswitches)*ord(PF_S))));
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end
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else if isabspowerof2(tordconstnode(right).value,power) then
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begin
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if (is_signed(right.resultdef)) then
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begin
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helper2:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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if power = 1 then
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helper1:=numerator
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else
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begin
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helper1:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,opsize,resultdef.size*8-1,numerator,helper1);
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end;
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shifterop_reset(so);
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so.shiftmode:=SM_LSR;
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so.shiftimm:=resultdef.size*8-power;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,helper2,numerator,helper1,so));
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SAR,def_cgsize(resultdef),power,helper2,resultreg);
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if (tordconstnode(right).value < 0) then
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{ Invert the result }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_NEG,resultreg,resultreg));
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end
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else
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,opsize,power,numerator,resultreg)
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end
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else
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{ Generic division }
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begin
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if is_signed(left.resultdef) then
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op:=A_SDIV
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else
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op:=A_UDIV;
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{ If we didn't acquire the original divisor earlier, grab it now }
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if divider = NR_NO then
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begin
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divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
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end;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,resultreg,numerator,divider));
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end;
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end;
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procedure genOverflowCheck;
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begin
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{ in case of overflow checking, also check for low(int64) div (-1)
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(no hardware support for this either) }
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if (cs_check_overflow in current_settings.localswitches) and
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is_signed(left.resultdef) and
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((right.nodetype<>ordconstn) or
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(tordconstnode(right).value=-1)) then
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begin
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{ num=ffff... and div=8000... <=>
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num xor not(div xor 8000...) = 0
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(and we have the "eon" operation, which performs "xor not(...)" }
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tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
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hlcg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_XOR,left.resultdef,low(int64),numerator,tmpreg);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_EON,
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tmpreg,numerator,tmpreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,tmpreg,0));
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{ now the zero/equal flag is set in case we divided low(int64) by
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(-1) }
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location_reset(overflowloc,LOC_FLAGS,OS_NO);
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overflowloc.resflags:=F_EQ;
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cg.g_overflowcheck_loc(current_asmdata.CurrAsmList,location,resultdef,overflowloc);
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end;
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end;
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begin
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secondpass(left);
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secondpass(right);
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{ avoid warning }
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divider := NR_NO;
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largernumreg := NR_NO;
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expandword := False;
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opsize := def_cgsize(resultdef);
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{ set result location }
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location_reset(location,LOC_REGISTER,opsize);
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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resultreg:=location.register;
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{ put numerator in register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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numerator:=left.location.register;
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if (right.nodetype=ordconstn) then
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begin
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{ If optimising for size, just use regular division operations }
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if (cs_opt_size in current_settings.optimizerswitches) or
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((tordconstnode(right).value=1) or
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(tordconstnode(right).value=int64(-1)) or
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isabspowerof2(tordconstnode(right).value,power)) then
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begin
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{ Store divisor for later (and executed at the same time as the multiplication) }
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if (nodetype=modn) then
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begin
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if (tordconstnode(right).value = 1) or (tordconstnode(right).value = int64(-1)) then
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begin
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{ Just evaluates to zero }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_MOVZ,resultreg, 0));
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Exit;
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end
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{ "not cs_opt_size" saves from checking the value of the divisor again
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(if cs_opt_size is not set, then the divisor is a power of 2) }
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else if not (cs_opt_size in current_settings.optimizerswitches) then
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begin
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divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
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end
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end;
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genOrdConstNodeDiv;
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genOverflowCheck;
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{ in case of modulo, multiply result again by the divider and subtract
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from the numerator }
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if (nodetype=modn) then
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begin
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if ispowerof2(tordconstnode(right).value,power) then
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begin
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shifterop.shiftmode := SM_LSL;
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shifterop.shiftimm := power;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_SUB,resultreg,numerator,resultreg,shifterop));
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_reg(A_MSUB,resultreg,
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resultreg,divider,numerator));
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end;
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Exit;
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end
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else
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begin
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if is_signed(left.resultdef) then
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begin
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if (nodetype=modn) then { Signed mod doesn't work properly }
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begin
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divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
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genOrdConstNodeDiv;
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end
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else
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begin
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{ Read signed value to avoid Internal Error 200706094 }
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dividend := tordconstnode(right).value.svalue;
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calc_divconst_magic_signed(resultdef.size * 8, dividend, reciprocal_signed, shift);
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cg.a_load_const_reg(current_asmdata.CurrAsmList, opsize, reciprocal_signed, resultreg);
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{ SMULH is only available for the full 64-bit registers }
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if opsize in [OS_64, OS_S64] then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SMULH,resultreg,resultreg,numerator));
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largerresreg := resultreg;
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end
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else
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begin
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largerresreg := newreg(getregtype(resultreg), getsupreg(resultreg), R_SUBWHOLE);
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largernumreg := newreg(getregtype(numerator), getsupreg(numerator), R_SUBWHOLE);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MUL,largerresreg,largerresreg,largernumreg));
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expandword := True; { Merge the shift operation with something below }
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end;
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{ Store divisor for later (and executed at the same time as the multiplication) }
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if nodetype=modn then
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begin
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divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,dividend,divider);
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end;
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{ add or subtract dividend }
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if (dividend > 0) and (reciprocal_signed < 0) then
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begin
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if expandword then
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begin
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shifterop.shiftmode := SM_ASR;
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shifterop.shiftimm := 32;
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expandword := False;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,largerresreg,largernumreg,largerresreg,shifterop));
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end
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ADD,resultreg,resultreg,numerator));
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end
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else if (dividend < 0) and (reciprocal_signed > 0) then
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begin
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if expandword then
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begin
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{ We can't append LSR to the SUB below because it's on the wrong operand }
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expandword := False;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_ASR,largerresreg,largerresreg,32));
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end;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUB,resultreg,resultreg,numerator));
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end
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else if expandword then
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Inc(shift,32);
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{ shift if necessary }
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if (shift <> 0) then
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begin
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if expandword then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_ASR,largerresreg,largerresreg,shift))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_ASR,resultreg,resultreg,shift));
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end;
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{ extract and add the sign bit }
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shifterop.shiftmode := SM_LSR;
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shifterop.shiftimm := left.resultdef.size*8 - 1;
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if (dividend < 0) then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,resultreg,resultreg,resultreg,shifterop))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ADD,resultreg,resultreg,numerator,shifterop));
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end;
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end
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else
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begin
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calc_divconst_magic_unsigned(resultdef.size * 8, tordconstnode(right).value, reciprocal, magic_add, shift);
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{ Add explicit typecast to tcgint type, to avoid range or overflow check }
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cg.a_load_const_reg(current_asmdata.CurrAsmList, opsize, tcgint(reciprocal), resultreg);
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{ UMULH is only available for the full 64-bit registers }
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if opsize in [OS_64, OS_S64] then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_UMULH,resultreg,resultreg,numerator));
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largerresreg := resultreg;
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end
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else
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begin
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largerresreg := newreg(getregtype(resultreg), getsupreg(resultreg), R_SUBWHOLE);
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largernumreg := newreg(getregtype(numerator), getsupreg(numerator), R_SUBWHOLE);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_MUL,largerresreg,largerresreg,largernumreg));
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expandword := True; { Try to merge the shift operation with something below }
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end;
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{ Store divisor for later (and executed at the same time as the multiplication) }
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if (nodetype=modn) then
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begin
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divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
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end;
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if magic_add then
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begin
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{ We can't append LSR to the ADD below because it would require extending the registers
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and interfere with the carry bit }
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if expandword then
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_LSR,largerresreg,largerresreg,32));
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{ Add the reciprocal to the high-order word, tracking the carry bit, shift, then
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insert the carry bit via CSEL and ORR }
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if opsize in [OS_64,OS_S64] then
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zeroreg := NR_XZR
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else
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zeroreg := NR_WZR;
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high_bit := QWord(1) shl ((resultdef.size * 8) - shift);
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tmpreg := cg.getintregister(current_asmdata.CurrAsmList, opsize);
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cg.a_load_const_reg(current_asmdata.CurrAsmList, opsize, high_bit, tmpreg);
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{ Generate ADDS instruction }
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hp := taicpu.op_reg_reg_reg(A_ADD,resultreg,resultreg,numerator);
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hp.oppostfix := PF_S;
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current_asmdata.CurrAsmList.concat(hp);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_cond(A_CSEL,tmpreg,tmpreg,zeroreg, C_CS));
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shifterop.shiftmode := SM_LSR;
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shifterop.shiftimm := shift;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_shifterop(A_ORR,resultreg,tmpreg,resultreg,shifterop));
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end
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else if expandword then
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{ Include the right-shift by 32 to get the high-order DWord }
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_LSR,largerresreg,largerresreg,shift + 32))
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_const(A_LSR,resultreg,resultreg,shift));
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end;
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end;
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end
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{ no divide-by-zero detection available in hardware, emulate (if it's a
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constant, this will have been detected earlier already) }
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else
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begin
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{ load divider in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,right.resultdef,true);
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divider:=right.location.register;
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{ ARM-64 developer guides recommend checking for division by zero conditions
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AFTER the division, since the check and the division can be done in tandem }
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if is_signed(left.resultdef) then
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op:=A_SDIV
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else
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op:=A_UDIV;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,resultreg,numerator,divider));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,divider,0));
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current_asmdata.getjumplabel(hl);
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current_asmdata.CurrAsmList.concat(taicpu.op_cond_sym(A_B,C_NE,hl));
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cg.a_call_name(current_asmdata.CurrAsmList,'FPC_DIVBYZERO',false);
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cg.a_label(current_asmdata.CurrAsmList,hl);
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end;
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genOverflowCheck;
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{ in case of modulo, multiply result again by the divider and subtract
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from the numerator }
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if (nodetype=modn) then
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begin
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{ If we didn't acquire the original divisor earlier, grab it now }
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if divider = NR_NO then
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begin
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divider:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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cg.a_load_const_reg(current_asmdata.CurrAsmList,opsize,tordconstnode(right).value.svalue,divider);
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end;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg_reg(A_MSUB,resultreg,
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resultreg,divider,numerator));
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end;
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end;
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{*****************************************************************************
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taarch64notnode
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*****************************************************************************}
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procedure taarch64notnode.second_boolean;
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begin
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secondpass(left);
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if not handle_locjump then
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begin
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case left.location.loc of
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LOC_FLAGS :
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begin
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location_copy(location,left.location);
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inverse_flags(location.resflags);
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end;
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LOC_REGISTER, LOC_CREGISTER,
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LOC_REFERENCE, LOC_CREFERENCE,
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LOC_SUBSETREG, LOC_CSUBSETREG,
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LOC_SUBSETREF, LOC_CSUBSETREF:
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,true);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_const(A_CMP,
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left.location.register,0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=F_EQ;
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end;
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else
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internalerror(2003042401);
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end;
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end;
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end;
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{*****************************************************************************
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taarch64unaryminusnode
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*****************************************************************************}
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procedure taarch64unaryminusnode.second_float;
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begin
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secondpass(left);
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hlcg.location_force_mmregscalar(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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location_reset(location,LOC_MMREGISTER,def_cgsize(resultdef));
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location.register:=cg.getmmregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FNEG,location.register,left.location.register));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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begin
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cmoddivnode:=taarch64moddivnode;
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cnotnode:=taarch64notnode;
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cunaryminusnode:=taarch64unaryminusnode;
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end.
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