mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-27 12:33:42 +02:00
9376f5a43a
o added AArch64 regset parsing support in assembler reader, means that "{"
no longer starts comments there (like in the ARM assembler reader)
o added AArch64 indexed SIMD register support and removed old cg hacks
that worked around its absence
git-svn-id: trunk@47116 -
101 lines
2.7 KiB
ObjectPascal
101 lines
2.7 KiB
ObjectPascal
{
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Copyright (c) 1998-2003 by Carl Eric Codere and Peter Vreman
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Copyright (c) 2014 by Jonas Maebe
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Handles the common AArch64 assembler reader routines
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit racpu;
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{$i fpcdefs.inc}
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interface
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uses
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cgbase,
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cpubase,
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aasmtai,aasmdata,
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rautils;
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type
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TAArch64Operand=class(TOperand)
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end;
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TAArch64Instruction=class(TInstruction)
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oppostfix : toppostfix;
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function ConcatInstruction(p:TAsmList) : tai;override;
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function Is64bit: boolean;
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function cgsize: tcgsize;
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end;
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implementation
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uses
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verbose,
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aasmcpu;
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function TAArch64Instruction.ConcatInstruction(p:TAsmList) : tai;
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begin
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result:=inherited ConcatInstruction(p);
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taicpu(result).oppostfix:=oppostfix;
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end;
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function TAArch64Instruction.Is64bit: boolean;
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begin
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result:=
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(operands[1].opr.typ=OPR_REGISTER) and
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(getsubreg(operands[1].opr.reg)=R_SUBQ);
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end;
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function TAArch64Instruction.cgsize: tcgsize;
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begin
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if ops<1 then
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internalerror(2014122001);
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if (ops=1) and (operands[1].opr.typ=OPR_REFERENCE) then
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exit(OS_NO);
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case operands[1].opr.typ of
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OPR_REGISTER:
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result:=reg_cgsize(operands[1].opr.reg);
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OPR_INDEXEDREG:
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result:=reg_cgsize(operands[1].opr.indexedreg);
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OPR_REGSET:
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result:=OS_NO;
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else
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internalerror(2014122002);
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end;
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{ a 32 bit integer register could actually be 16 or 8 bit }
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if result=OS_32 then
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case oppostfix of
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PF_NONE: ;
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PF_B:
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result:=OS_8;
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PF_SB:
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result:=OS_S8;
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PF_H:
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result:=OS_16;
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PF_SH:
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result:=OS_S16;
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else
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Message(asmr_e_invalid_opcode_and_operand)
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end;
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end;
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end.
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