fpc/compiler/riscv
Jonas Maebe 07bd4ba517 * let all the case code generation work with tconstexprint instead of aint,
so it also works for 32 bit targets and a high level code generator
    (where aint is still 32 bit, but 64 bit operations are not decomposed)

git-svn-id: trunk@41441 -
2019-02-24 19:58:37 +00:00
..
aasmcpu.pas
agrvgas.pas
cgrv.pas
hlcgrv.pas
nrvadd.pas Fix riscv32 compilation error introduced in last commit 2018-11-16 10:24:27 +00:00
nrvcnv.pas
nrvcon.pas
nrvinl.pas
nrvset.pas * let all the case code generation work with tconstexprint instead of aint, 2019-02-24 19:58:37 +00:00
rgcpu.pas