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589 lines
18 KiB
ObjectPascal
589 lines
18 KiB
ObjectPascal
{
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This file is part of the Free Pascal run time library.
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Copyright (c) 2014 by Free Pascal development team
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hardware definitions
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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{
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registers and bits in the Complex Interface Adapter (CIA) chip
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}
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unit hardware;
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interface
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uses
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Exec;
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{
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* ciaa is on an ODD Pointer (e.g. the low Byte) -- $bfe001
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* ciab is on an EVEN Pointer (e.g. the high Byte) -- $bfd000
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*
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* do this to get the definitions:
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* extern struct CIA ciaa, ciab;
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}
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Type
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pCIA = ^tCIA;
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tCIA = record
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ciapra : Byte;
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pad0 : Array [0..254] of Byte;
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ciaprb : Byte;
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pad1 : Array [0..254] of Byte;
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ciaddra : Byte;
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pad2 : Array [0..254] of Byte;
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ciaddrb : Byte;
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pad3 : Array [0..254] of Byte;
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ciatalo : Byte;
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pad4 : Array [0..254] of Byte;
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ciatahi : Byte;
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pad5 : Array [0..254] of Byte;
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ciatblo : Byte;
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pad6 : Array [0..254] of Byte;
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ciatbhi : Byte;
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pad7 : Array [0..254] of Byte;
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ciatodlow : Byte;
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pad8 : Array [0..254] of Byte;
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ciatodmid : Byte;
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pad9 : Array [0..254] of Byte;
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ciatodhi : Byte;
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pad10 : Array [0..254] of Byte;
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unusedreg : Byte;
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pad11 : Array [0..254] of Byte;
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ciasdr : Byte;
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pad12 : Array [0..254] of Byte;
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ciaicr : Byte;
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pad13 : Array [0..254] of Byte;
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ciacra : Byte;
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pad14 : Array [0..254] of Byte;
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ciacrb : Byte;
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end;
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Const
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{ interrupt control register bit numbers }
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CIAICRB_TA = 0;
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CIAICRB_TB = 1;
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CIAICRB_ALRM = 2;
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CIAICRB_SP = 3;
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CIAICRB_FLG = 4;
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CIAICRB_IR = 7;
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CIAICRB_SETCLR = 7;
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{ control register A bit numbers }
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CIACRAB_START = 0;
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CIACRAB_PBON = 1;
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CIACRAB_OUTMODE = 2;
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CIACRAB_RUNMODE = 3;
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CIACRAB_LOAD = 4;
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CIACRAB_INMODE = 5;
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CIACRAB_SPMODE = 6;
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CIACRAB_TODIN = 7;
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{ control register B bit numbers }
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CIACRBB_START = 0;
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CIACRBB_PBON = 1;
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CIACRBB_OUTMODE = 2;
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CIACRBB_RUNMODE = 3;
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CIACRBB_LOAD = 4;
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CIACRBB_INMODE0 = 5;
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CIACRBB_INMODE1 = 6;
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CIACRBB_ALARM = 7;
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{ interrupt control register masks }
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CIAICRF_TA = $01;
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CIAICRF_TB = $02;
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CIAICRF_ALRM = $04;
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CIAICRF_SP = $08;
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CIAICRF_FLG = $10;
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CIAICRF_IR = $80;
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CIAICRF_SETCLR = $80;
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{ control register A register masks }
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CIACRAF_START = $01;
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CIACRAF_PBON = $02;
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CIACRAF_OUTMODE = $04;
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CIACRAF_RUNMODE = $08;
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CIACRAF_LOAD = $10;
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CIACRAF_INMODE = $20;
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CIACRAF_SPMODE = $40;
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CIACRAF_TODIN = $80;
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{ control register B register masks }
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CIACRBF_START = $01;
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CIACRBF_PBON = $02;
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CIACRBF_OUTMODE = $04;
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CIACRBF_RUNMODE = $08;
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CIACRBF_LOAD = $10;
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CIACRBF_INMODE0 = $20;
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CIACRBF_INMODE1 = $40;
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CIACRBF_ALARM = $80;
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{ control register B INMODE masks }
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CIACRBF_IN_PHI2 = 0;
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CIACRBF_IN_CNT = CIACRBF_INMODE0;
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CIACRBF_IN_TA = CIACRBF_INMODE1;
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CIACRBF_IN_CNT_TA = CIACRBF_INMODE0 + CIACRBF_INMODE1;
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{
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* Port definitions -- what each bit in a cia peripheral register is tied to
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}
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{ ciaa port A (0xbfe001) }
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CIAB_GAMEPORT1 = 7; { gameport 1, pin 6 (fire button*) }
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CIAB_GAMEPORT0 = 6; { gameport 0, pin 6 (fire button*) }
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CIAB_DSKRDY = 5; { disk ready* }
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CIAB_DSKTRACK0 = 4; { disk on track 00* }
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CIAB_DSKPROT = 3; { disk write protect* }
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CIAB_DSKCHANGE = 2; { disk change* }
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CIAB_LED = 1; { led light control (0==>bright) }
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CIAB_OVERLAY = 0; { memory overlay bit }
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{ ciaa port B (0xbfe101) -- parallel port }
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{ ciab port A (0xbfd000) -- serial and printer control }
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CIAB_COMDTR = 7; { serial Data Terminal Ready* }
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CIAB_COMRTS = 6; { serial Request to Send* }
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CIAB_COMCD = 5; { serial Carrier Detect* }
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CIAB_COMCTS = 4; { serial Clear to Send* }
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CIAB_COMDSR = 3; { serial Data Set Ready* }
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CIAB_PRTRSEL = 2; { printer SELECT }
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CIAB_PRTRPOUT = 1; { printer paper out }
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CIAB_PRTRBUSY = 0; { printer busy }
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{ ciab port B (0xbfd100) -- disk control }
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CIAB_DSKMOTOR = 7; { disk motorr* }
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CIAB_DSKSEL3 = 6; { disk select unit 3* }
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CIAB_DSKSEL2 = 5; { disk select unit 2* }
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CIAB_DSKSEL1 = 4; { disk select unit 1* }
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CIAB_DSKSEL0 = 3; { disk select unit 0* }
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CIAB_DSKSIDE = 2; { disk side select* }
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CIAB_DSKDIREC = 1; { disk direction of seek* }
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CIAB_DSKSTEP = 0; { disk step heads* }
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{ ciaa port A (0xbfe001) }
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CIAF_GAMEPORT1 = 128;
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CIAF_GAMEPORT0 = 64;
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CIAF_DSKRDY = 32;
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CIAF_DSKTRACK0 = 16;
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CIAF_DSKPROT = 8;
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CIAF_DSKCHANGE = 4;
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CIAF_LED = 2;
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CIAF_OVERLAY = 1;
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{ ciaa port B (0xbfe101) -- parallel port }
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{ ciab port A (0xbfd000) -- serial and printer control }
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CIAF_COMDTR = 128;
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CIAF_COMRTS = 64;
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CIAF_COMCD = 32;
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CIAF_COMCTS = 16;
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CIAF_COMDSR = 8;
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CIAF_PRTRSEL = 4;
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CIAF_PRTRPOUT = 2;
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CIAF_PRTRBUSY = 1;
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{ ciab port B (0xbfd100) -- disk control }
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CIAF_DSKMOTOR = 128;
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CIAF_DSKSEL3 = 64;
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CIAF_DSKSEL2 = 32;
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CIAF_DSKSEL1 = 16;
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CIAF_DSKSEL0 = 8;
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CIAF_DSKSIDE = 4;
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CIAF_DSKDIREC = 2;
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CIAF_DSKSTEP = 1;
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Type
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pAudChannel = ^tAudChannel;
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tAudChannel = record
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ac_ptr : Pointer; { ptr to start of waveform data }
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ac_len : Word; { length of waveform in words }
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ac_per : Word; { sample period }
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ac_vol : Word; { volume }
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ac_dat : Word; { sample pair }
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ac_pad : Array [0..1] of Word; { unused }
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end;
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pSpriteDef = ^tSpriteDef;
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tSpriteDef = record
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pos : Word;
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ctl : Word;
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dataa : Word;
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datab : Word;
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end;
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pCustom = ^tCustom;
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tCustom = record
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bltddat : Word;
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dmaconr : Word;
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vposr : Word;
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vhposr : Word;
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dskdatr : Word;
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joy0dat : Word;
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joy1dat : Word;
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clxdat : Word;
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adkconr : Word;
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pot0dat : Word;
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pot1dat : Word;
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potinp : Word;
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serdatr : Word;
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dskbytr : Word;
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intenar : Word;
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intreqr : Word;
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dskpt : Pointer;
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dsklen : Word;
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dskdat : Word;
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refptr : Word;
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vposw : Word;
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vhposw : Word;
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copcon : Word;
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serdat : Word;
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serper : Word;
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potgo : Word;
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joytest : Word;
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strequ : Word;
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strvbl : Word;
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strhor : Word;
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strlong : Word;
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bltcon0 : Word;
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bltcon1 : Word;
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bltafwm : Word;
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bltalwm : Word;
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bltcpt : Pointer;
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bltbpt : Pointer;
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bltapt : Pointer;
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bltdpt : Pointer;
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bltsize : Word;
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pad2d : Byte;
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bltcon0l : Byte;
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bltsizv : Word;
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bltsizh : Word;
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bltcmod : Word;
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bltbmod : Word;
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bltamod : Word;
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bltdmod : Word;
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pad34 : Array [0..3] of Word;
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bltcdat : Word;
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bltbdat : Word;
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bltadat : Word;
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pad3b : Array [0..2] of Word;
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deniseid : Word;
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dsksync : Word;
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cop1lc : Longint;
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cop2lc : Longint;
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copjmp1 : Word;
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copjmp2 : Word;
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copins : Word;
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diwstrt : Word;
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diwstop : Word;
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ddfstrt : Word;
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ddfstop : Word;
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dmacon : Word;
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clxcon : Word;
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intena : Word;
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intreq : Word;
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adkcon : Word;
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aud : Array [0..3] of tAudChannel;
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bplpt : Array [0..7] of Pointer;
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bplcon0 : Word;
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bplcon1 : Word;
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bplcon2 : Word;
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bplcon3 : Word;
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bpl1mod : Word;
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bpl2mod : Word;
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bplcon4 : Word;
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clxcon2 : Word;
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bpldat : Array [0..7] of Word;
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sprpt : Array [0..7] of Pointer;
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spr : Array [0..7] of tSpriteDef;
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color : Array [0..31] of Word;
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htotal : Word;
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hsstop : Word;
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hbstrt : Word;
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hbstop : Word;
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vtotal : Word;
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vsstop : Word;
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vbstrt : Word;
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vbstop : Word;
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sprhstrt : Word;
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sprhstop : Word;
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bplhstrt : Word;
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bplhstop : Word;
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hhposw : Word;
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hhposr : Word;
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beamcon0 : Word;
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hsstrt : Word;
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vsstrt : Word;
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hcenter : Word;
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diwhigh : Word;
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padf3 : Array [0..10] of Word;
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fmode : Word;
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end;
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CONST
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{ defines for beamcon register }
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VARVBLANK = $1000; { Variable vertical blank enable }
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LOLDIS = $0800; { long line disable }
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CSCBLANKEN = $0400; { redirect composite sync }
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VARVSYNC = $0200; { Variable vertical sync enable }
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VARHSYNC = $0100; { Variable horizontal sync enable }
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VARBEAM = $0080; { variable beam counter enable }
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DISPLAYDUAL = $0040; { use UHRES pointer AND standard pointers }
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DISPLAYPAL = $0020; { set decodes to generate PAL display }
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VARCSYNC = $0010; { Variable composite sync enable }
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CSBLANK = $0008; { Composite blank out to CSY* pin }
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CSYNCTRUE = $0004; { composite sync TRUE signal }
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VSYNCTRUE = $0002; { vertical sync TRUE }
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HSYNCTRUE = $0001; { horizontal sync TRUE }
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{ new defines for bplcon0 }
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USE_BPLCON3 = 1;
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{ new defines for bplcon2 }
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BPLCON2_ZDCTEN = 1024; { colormapped genlock bit }
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BPLCON2_ZDBPEN = 2048; { use bitplane as genlock bits }
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BPLCON2_ZDBPSEL0 = 4096; { three bits to select one }
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BPLCON2_ZDBPSEL1 = 8192; { of 8 bitplanes in }
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BPLCON2_ZDBPSEL2 = 16384; { ZDBPEN genlock mode }
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{ defines for bplcon3 register }
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BPLCON3_EXTBLNKEN = 1; { external blank enable }
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BPLCON3_EXTBLKZD = 2; { external blank ored into trnsprncy }
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BPLCON3_ZDCLKEN = 4; { zd pin outputs a 14mhz clock}
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BPLCON3_BRDNTRAN = 16; { border is opaque }
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BPLCON3_BRDNBLNK = 32; { border is opaque }
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Const
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ADKB_SETCLR = 15; { standard set/clear bit }
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ADKB_PRECOMP1 = 14; { two bits of precompensation }
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ADKB_PRECOMP0 = 13;
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ADKB_MFMPREC = 12; { use mfm style precompensation }
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ADKB_UARTBRK = 11; { force uart output to zero }
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ADKB_WORDSYNC = 10; { enable DSKSYNC register matching }
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ADKB_MSBSYNC = 9; { (Apple GCR Only) sync on MSB for reading }
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ADKB_FAST = 8; { 1 -> 2 us/bit (mfm), 2 -> 4 us/bit (gcr) }
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ADKB_USE3PN = 7; { use aud chan 3 to modulate period of ?? }
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ADKB_USE2P3 = 6; { use aud chan 2 to modulate period of 3 }
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ADKB_USE1P2 = 5; { use aud chan 1 to modulate period of 2 }
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ADKB_USE0P1 = 4; { use aud chan 0 to modulate period of 1 }
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ADKB_USE3VN = 3; { use aud chan 3 to modulate volume of ?? }
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ADKB_USE2V3 = 2; { use aud chan 2 to modulate volume of 3 }
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ADKB_USE1V2 = 1; { use aud chan 1 to modulate volume of 2 }
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ADKB_USE0V1 = 0; { use aud chan 0 to modulate volume of 1 }
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ADKF_SETCLR = $8000;
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ADKF_PRECOMP1 = $4000;
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ADKF_PRECOMP0 = $2000;
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ADKF_MFMPREC = $1000;
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ADKF_UARTBRK = $0800;
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ADKF_WORDSYNC = $0400;
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ADKF_MSBSYNC = $0200;
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ADKF_FAST = $0100;
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ADKF_USE3PN = $0080;
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ADKF_USE2P3 = $0040;
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ADKF_USE1P2 = $0020;
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ADKF_USE0P1 = $0010;
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ADKF_USE3VN = $0008;
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ADKF_USE2V3 = $0004;
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ADKF_USE1V2 = $0002;
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ADKF_USE0V1 = $0001;
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ADKF_PRE000NS = 0; { 000 ns of precomp }
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ADKF_PRE140NS = ADKF_PRECOMP0; { 140 ns of precomp }
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ADKF_PRE280NS = ADKF_PRECOMP1; { 280 ns of precomp }
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ADKF_PRE560NS = ADKF_PRECOMP0 + ADKF_PRECOMP1; { 560 ns of precomp }
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Const
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HSIZEBITS = 6;
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VSIZEBITS = 16 - HSIZEBITS;
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HSIZEMASK = $3F; { 2^6 - 1 }
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VSIZEMASK = $3FF; { 2^10 - 1 }
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MAXBYTESPERROW = 128;
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{ definitions for blitter control register 0 }
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ABC = $80;
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ABNC = $40;
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ANBC = $20;
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ANBNC = $10;
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NABC = $08;
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NABNC = $04;
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NANBC = $02;
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NANBNC = $01;
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{ some commonly used operations }
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A_OR_B = ABC + ANBC + NABC + ABNC + ANBNC + NABNC;
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A_OR_C = ABC + NABC + ABNC + ANBC + NANBC + ANBNC;
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A_XOR_C = NABC + ABNC + NANBC + ANBNC;
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A_TO_D = ABC + ANBC + ABNC + ANBNC;
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BC0B_DEST = 8;
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BC0B_SRCC = 9;
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BC0B_SRCB = 10;
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BC0B_SRCA = 11;
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BC0F_DEST = $100;
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BC0F_SRCC = $200;
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BC0F_SRCB = $400;
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BC0F_SRCA = $800;
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BC1F_DESC = 2; { blitter descend direction }
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DEST = $100;
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SRCC = $200;
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SRCB = $400;
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SRCA = $800;
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ASHIFTSHIFT = 12; { bits to right align ashift value }
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BSHIFTSHIFT = 12; { bits to right align bshift value }
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{ definations for blitter control register 1 }
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LINEMODE = $01;
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FILL_OR = $08;
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FILL_XOR = $10;
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FILL_CARRYIN = $04;
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ONEDOT = $02; { one dot per horizontal line }
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OVFLAG = $20;
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SIGNFLAG = $40;
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BLITREVERSE = $02;
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SUD = $10;
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SUL = $08;
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AUL = $04;
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OCTANT8 = 24;
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OCTANT7 = 4;
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OCTANT6 = 12;
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OCTANT5 = 28;
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OCTANT4 = 20;
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OCTANT3 = 8;
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OCTANT2 = 0;
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OCTANT1 = 16;
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type
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PBltNode = ^TBltNode;
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TBltNode = record
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n: Pbltnode;
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function_: Pointer;
|
|
Stat: Byte;
|
|
BltSize: SmallInt;
|
|
BeamSync: smallint;
|
|
CleanUp: Pointer;
|
|
end;
|
|
|
|
Const
|
|
|
|
{ write definitions for dmaconw }
|
|
|
|
DMAF_SETCLR = $8000;
|
|
DMAF_AUDIO = $000F; { 4 bit mask }
|
|
DMAF_AUD0 = $0001;
|
|
DMAF_AUD1 = $0002;
|
|
DMAF_AUD2 = $0004;
|
|
DMAF_AUD3 = $0008;
|
|
DMAF_DISK = $0010;
|
|
DMAF_SPRITE = $0020;
|
|
DMAF_BLITTER = $0040;
|
|
DMAF_COPPER = $0080;
|
|
DMAF_RASTER = $0100;
|
|
DMAF_MASTER = $0200;
|
|
DMAF_BLITHOG = $0400;
|
|
DMAF_ALL = $01FF; { all dma channels }
|
|
|
|
{ read definitions for dmaconr }
|
|
{ bits 0-8 correspnd to dmaconw definitions }
|
|
|
|
DMAF_BLTDONE = $4000;
|
|
DMAF_BLTNZERO = $2000;
|
|
|
|
DMAB_SETCLR = 15;
|
|
DMAB_AUD0 = 0;
|
|
DMAB_AUD1 = 1;
|
|
DMAB_AUD2 = 2;
|
|
DMAB_AUD3 = 3;
|
|
DMAB_DISK = 4;
|
|
DMAB_SPRITE = 5;
|
|
DMAB_BLITTER = 6;
|
|
DMAB_COPPER = 7;
|
|
DMAB_RASTER = 8;
|
|
DMAB_MASTER = 9;
|
|
DMAB_BLITHOG = 10;
|
|
DMAB_BLTDONE = 14;
|
|
DMAB_BLTNZERO = 13;
|
|
|
|
|
|
Const
|
|
|
|
INTB_SETCLR = 15; { Set/Clear control bit. Determines if bits }
|
|
{ written with a 1 get set or cleared. Bits }
|
|
{ written with a zero are allways unchanged }
|
|
INTB_INTEN = 14; { Master interrupt (enable only ) }
|
|
INTB_EXTER = 13; { External interrupt }
|
|
INTB_DSKSYNC = 12; { Disk re-SYNChronized }
|
|
INTB_RBF = 11; { serial port Receive Buffer Full }
|
|
INTB_AUD3 = 10; { Audio channel 3 block finished }
|
|
INTB_AUD2 = 9; { Audio channel 2 block finished }
|
|
INTB_AUD1 = 8; { Audio channel 1 block finished }
|
|
INTB_AUD0 = 7; { Audio channel 0 block finished }
|
|
INTB_BLIT = 6; { Blitter finished }
|
|
INTB_VERTB = 5; { start of Vertical Blank }
|
|
INTB_COPER = 4; { Coprocessor }
|
|
INTB_PORTS = 3; { I/O Ports and timers }
|
|
INTB_SOFTINT = 2; { software interrupt request }
|
|
INTB_DSKBLK = 1; { Disk Block done }
|
|
INTB_TBE = 0; { serial port Transmit Buffer Empty }
|
|
|
|
|
|
INTF_SETCLR = $8000;
|
|
INTF_INTEN = $4000;
|
|
INTF_EXTER = $2000;
|
|
INTF_DSKSYNC = $1000;
|
|
INTF_RBF = $0800;
|
|
INTF_AUD3 = $0400;
|
|
INTF_AUD2 = $0200;
|
|
INTF_AUD1 = $0100;
|
|
INTF_AUD0 = $0080;
|
|
INTF_BLIT = $0040;
|
|
INTF_VERTB = $0020;
|
|
INTF_COPER = $0010;
|
|
INTF_PORTS = $0008;
|
|
INTF_SOFTINT = $0004;
|
|
INTF_DSKBLK = $0002;
|
|
INTF_TBE = $0001;
|
|
|
|
IMPLEMENTATION
|
|
|
|
end.
|