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6f5a648516
Therefor the cpu type (-Cp...) "coldfire" was split up into "isaa", "isaa+", "isab" and "isac". The Linux RTL can currently compiled for "68020", "isab" and "isac". For the other three Bcc.L must be handled differently (only Bcc.B/W supported) and for "68000" also EXT.L needs to be handled differently. fpcdefs.inc: + define CPUCAPABILITIES if capabilities can be set for a certain CPU type (currently ARM, AVR and M68k) options.pas: * check for CPUCAPABILITIES instead of specific CPUs assemble.pas: - the handling of the CPU type is already done in m68k/ag68kgas.pas, Tm68kGNUAssembler.MakeCmdLine (and thereby already using the gascputypestr array!) m68k/cpuinfo.pas: - tcputype: remove "cpu_coldfire" + tcputype: add "cpu_isa_a", "cpu_isa_a_p", "cpu_isa_b" and "cpu_isa_c" + add "cpu_coldfire" constant which contains all Coldfire specific cpu types * adjust "cputypestr" and "gascputypestr" + add tcpuflags and cpu_capabilities (DBRA restriction was checked with CPUCOLDFIRE, CAS/TAS will be needed for atomic operations and BRAL restriction was discovered during testing of new cpu types) m68k/cgcpu.pas: * adjust checks for "cpu_coldfire" m68k/n68kadd.pas: * don't use a BRA.L if it is not supported, but (at least for now) a BRA.W aggas.pas: * adjusted check for Coldfire git-svn-id: trunk@25457 -
127 lines
3.6 KiB
ObjectPascal
127 lines
3.6 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by the Free Pascal development team
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Basic Processor information for the m68k
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See the file COPYING.FPC, included in this distribution,
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for details about the copyright.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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**********************************************************************}
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Unit CPUInfo;
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Interface
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uses
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globtype;
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Type
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bestreal = double;
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ts32real = single;
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ts64real = double;
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ts80real = extended;
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ts128real = type extended;
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ts64comp = extended;
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pbestreal=^bestreal;
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{ possible supported processors for this target }
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tcputype =
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(cpu_none,
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cpu_MC68000,
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cpu_MC68020,
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cpu_isa_a,
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cpu_isa_a_p,
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cpu_isa_b,
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cpu_isa_c
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);
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tfputype =
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(fpu_none,
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fpu_soft,
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fpu_libgcc,
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fpu_68881
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);
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Const
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{ calling conventions supported by the code generator }
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supported_calling_conventions : tproccalloptions = [
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pocall_internproc,
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pocall_stdcall,
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{ the difference to stdcall is only the name mangling }
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pocall_cdecl,
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{ the difference to stdcall is only the name mangling }
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pocall_cppdecl,
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{ this used by the PalmOS port only }
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pocall_syscall
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];
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cputypestr : array[tcputype] of string[8] = ('',
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'68000',
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'68020',
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'ISAA',
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'ISAA+',
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'ISAB',
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'ISAC'
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);
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gascputypestr : array[tcputype] of string[8] = ('',
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'68000',
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'68020',
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'isaa',
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'isaaplus',
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'isab',
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'isac'
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);
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fputypestr : array[tfputype] of string[6] = ('',
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'SOFT',
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'LIBGCC',
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'68881'
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);
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = genericlevel1optimizerswitches+
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genericlevel2optimizerswitches+
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genericlevel3optimizerswitches-
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{ no need to write info about those }
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[cs_opt_level1,cs_opt_level2,cs_opt_level3]+
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[cs_opt_regvar,cs_opt_loopunroll,cs_opt_nodecse,
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cs_opt_reorder_fields,cs_opt_fastmath];
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level1optimizerswitches = genericlevel1optimizerswitches;
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level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
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[cs_opt_regvar,cs_opt_stackframe,cs_opt_nodecse];
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level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches + [{,cs_opt_loopunroll}];
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level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [];
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type
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tcpuflags =
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(CPUM68K_HAS_DBRA, { CPU supports the DBRA instruction }
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CPUM68K_HAS_CAS, { CPU supports the CAS instruction }
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CPUM68K_HAS_TAS, { CPU supports the TAS instruction }
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CPUM68K_HAS_BRAL { CPU supports the BRA.L/Bcc.L instructions }
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);
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags =
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( { cpu_none } [],
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{ cpu_68000 } [CPUM68K_HAS_DBRA,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL],
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{ cpu_68020 } [CPUM68K_HAS_DBRA,CPUM68K_HAS_CAS,CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL],
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{ cpu_isaa } [],
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{ cpu_isaap } [CPUM68K_HAS_BRAL],
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{ cpu_isab } [CPUM68K_HAS_TAS,CPUM68K_HAS_BRAL],
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{ cpu_isac } [CPUM68K_HAS_TAS]
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);
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{ all CPUs commonly cold "coldfire" }
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cpu_coldfire = [cpu_isa_a,cpu_isa_a_p,cpu_isa_b,cpu_isa_c];
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Implementation
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end.
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