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513 lines
22 KiB
ObjectPascal
513 lines
22 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Jonas Maebe, member of the Free Pascal
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Development Team
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This unit implements the PowerPC optimizer object
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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Unit aoptcpu;
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Interface
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{$i fpcdefs.inc}
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uses cpubase, cgbase, aoptobj, aoptcpub, aopt, aasmtai,aasmdata, aasmcpu, aoptppc;
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Type
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TCpuAsmOptimizer = class(TPPCAsmOptimizer)
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{ uses the same constructor as TAopObj }
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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function PostPeepHoleOptsCpu(var p: tai): boolean; override;
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private
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function cmpi_mfcr_opt(p, next1, next2: taicpu): boolean;
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End;
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Implementation
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uses
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cutils, verbose, cgcpu, cgobj;
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function TCpuAsmOptimizer.cmpi_mfcr_opt(p, next1, next2: taicpu): boolean;
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var
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next3, prev: tai;
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inverse, prevrlwinm: boolean;
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begin
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result := true;
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inverse :=
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getnextinstruction(next2,next3) and
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(next3.typ = ait_instruction) and
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(taicpu(next3).opcode = A_XORI) and
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(taicpu(next3).oper[0]^.reg = taicpu(next3).oper[1]^.reg) and
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(taicpu(next3).oper[0]^.reg = taicpu(next2).oper[0]^.reg) and
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(taicpu(next3).oper[2]^.val = 1);
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case taicpu(next2).oper[2]^.val of
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1:
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begin
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// less than zero or greater/equal than zero (the xori remains in
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// in the latter case). Doesn't make sense for unsigned comparisons.
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if (p.opcode = A_CMPWI) then
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begin
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p.opcode := A_SRWI;
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p.ops := 3;
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p.loadreg(1,p.oper[0]^.reg);
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p.loadreg(0,next1.oper[0]^.reg);
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p.loadconst(2,31);
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asml.remove(next1);
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next1.free;
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asml.remove(next2);
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next2.free;
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end
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else
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result := false;
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end;
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{
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needs two registers to work with
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2:
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begin
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// greater or less/equal to zero
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end;
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}
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3:
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begin
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prevrlwinm :=
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getlastinstruction(p,prev) and
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(prev.typ = ait_instruction) and
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((taicpu(prev).opcode = A_RLWINM) or
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(taicpu(prev).opcode = A_RLWINM_)) and
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(taicpu(prev).oper[0]^.reg = p.oper[0]^.reg) and
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(taicpu(prev).oper[3]^.val = taicpu(prev).oper[4]^.val);
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if (prevrlwinm) then
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begin
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// isolate the bit we need
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if (taicpu(prev).oper[3]^.val <> 31) then
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begin
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p.opcode := A_RLWINM;
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p.ops := 5;
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p.loadreg(1,p.oper[0]^.reg);
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p.loadreg(0,next1.oper[0]^.reg);
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p.loadconst(2,taicpu(prev).oper[3]^.val + 1);
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p.loadconst(3,31);
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p.loadconst(4,31);
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end
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else { if (taicpu(prev).oper[0]^.reg <> next1.oper[0]^.reg) then }
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begin
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p.opcode := A_MR;
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p.loadreg(1,p.oper[0]^.reg);
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p.loadreg(0,next1.oper[0]^.reg);
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end;
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if not inverse then
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begin
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next1.ops := 3;
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next1.opcode := A_XORI;
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next1.loadreg(1,next1.oper[0]^.reg);
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next1.loadconst(2,1);
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end
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else
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begin
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asml.remove(next1);
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next1.free;
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asml.remove(next3);
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next3.free;
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end;
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asml.remove(next2);
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next2.free;
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end
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else
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begin
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// equal/not equal to zero (the xori remains in the latter case;
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// there's a more optimal sequence without it, but needs extra
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// register)
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p.opcode := A_CNTLZW;
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p.loadreg(1,p.oper[0]^.reg);
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p.loadreg(0,next1.oper[0]^.reg);
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next1.ops := 3;
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next1.opcode := A_SRWI;
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next1.loadreg(1,next1.oper[0]^.reg);
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next1.loadconst(2,5);
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asml.remove(next2);
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next2.free;
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end;
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end;
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else
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result := false;
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end;
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end;
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function rlwinm2mask(l1,l2: longint): longint;
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begin
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// 1 shl 32 = 1 instead of 0 on x86
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if (l1 <> 0) then
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result := longint(cardinal(1) shl (32 - l1) - 1) xor (cardinal(1) shl (31 - l2) - 1)
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else
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result := longint(not(cardinal(1) shl (31 - l2) - 1));
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if (l1 > l2) then
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result := not(result);
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end;
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function TCpuAsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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var
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next1, next2: tai;
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l1, l2, shlcount: longint;
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begin
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result := false;
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case p.typ of
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ait_instruction:
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begin
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case taicpu(p).opcode of
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A_CMPWI,
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A_CMPLWI:
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begin
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if (taicpu(p).oper[1]^.typ = top_const) and
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(taicpu(p).oper[1]^.val = 0) and
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getnextinstruction(p,next1) and
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(next1.typ = ait_instruction) and
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(taicpu(next1).opcode = A_MFCR) and
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getnextinstruction(next1,next2) and
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(taicpu(next2).opcode = A_RLWINM) and
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(taicpu(next2).oper[0]^.reg = taicpu(next2).oper[1]^.reg) and
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(taicpu(next2).oper[0]^.reg = taicpu(next1).oper[0]^.reg) and
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(taicpu(next2).oper[3]^.val = 31) and
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(taicpu(next2).oper[4]^.val = 31) and
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cmpi_mfcr_opt(taicpu(p),taicpu(next1),taicpu(next2)) then
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result := true;
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end;
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{ seems the register allocator doesn't generate superfluous fmr's }
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{ A_FMR, }
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A_MR:
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begin
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if getnextinstruction(p,next1) and
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(next1.typ = ait_instruction) and
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(taicpu(next1).ops >= 1) and
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{ spilling_get_operation_type does not support lmw/stmw }
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(taicpu(next1).opcode <> A_LMW) and
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(taicpu(next1).opcode <> A_STMW) and
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(taicpu(next1).spilling_get_operation_type(0) = operand_write) and
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(taicpu(next1).oper[0]^.reg = taicpu(p).oper[0]^.reg) then
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begin
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for l1 := 1 to taicpu(next1).ops - 1 do
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case taicpu(next1).oper[l1]^.typ of
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top_reg:
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if taicpu(next1).oper[l1]^.reg = taicpu(p).oper[0]^.reg then
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taicpu(next1).loadreg(l1,taicpu(p).oper[1]^.reg);
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top_ref:
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begin
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if taicpu(next1).oper[l1]^.ref^.base = taicpu(p).oper[0]^.reg then
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taicpu(next1).oper[l1]^.ref^.base := taicpu(p).oper[1]^.reg;
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if taicpu(next1).oper[l1]^.ref^.index = taicpu(p).oper[0]^.reg then
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taicpu(next1).oper[l1]^.ref^.index := taicpu(p).oper[1]^.reg;
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end;
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else
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;
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end;
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asml.remove(p);
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p.free;
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p := next1;
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result := true;
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end;
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end;
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A_SLWI:
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begin
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if getnextinstruction(p,next1) and
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(next1.typ = ait_instruction) and
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((taicpu(next1).opcode = A_RLWINM) or
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(taicpu(next1).opcode = A_SLWI) or
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(taicpu(next1).opcode = A_SRWI)) and
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(taicpu(next1).oper[0]^.reg = taicpu(p).oper[0]^.reg) and
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(taicpu(next1).oper[1]^.reg = taicpu(p).oper[0]^.reg) then
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begin
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{ convert slwi to rlwinm and see if the rlwinm }
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{ optimization can do something with it }
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taicpu(p).opcode := A_RLWINM;
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taicpu(p).ops := 5;
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taicpu(p).loadconst(2,taicpu(p).oper[2]^.val);
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taicpu(p).loadconst(3,0);
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taicpu(p).loadconst(4,31-taicpu(p).oper[2]^.val);
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result := true;
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end;
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end;
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A_SRWI:
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begin
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if getnextinstruction(p,next1) and
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(next1.typ = ait_instruction) and
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((taicpu(next1).opcode = A_SLWI) or
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(taicpu(next1).opcode = A_RLWINM) or
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(taicpu(next1).opcode = A_SRWI)) and
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(taicpu(next1).oper[0]^.reg = taicpu(p).oper[0]^.reg) and
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(taicpu(next1).oper[1]^.reg = taicpu(p).oper[0]^.reg) then
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case taicpu(next1).opcode of
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A_SLWI:
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begin
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taicpu(p).opcode := A_RLWINM;
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taicpu(p).ops := 5;
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taicpu(p).loadconst(2,taicpu(next1).oper[2]^.val-taicpu(p).oper[2]^.val);
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if (taicpu(p).oper[2]^.val < 0) then
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begin
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taicpu(p).loadconst(3,-taicpu(p).oper[2]^.val);
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taicpu(p).loadconst(4,31-taicpu(next1).oper[2]^.val);
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inc(taicpu(p).oper[2]^.val,32);
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end
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else
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begin
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taicpu(p).loadconst(3,0);
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taicpu(p).loadconst(4,31-taicpu(next1).oper[2]^.val);
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end;
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asml.remove(next1);
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next1.free;
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result := true;
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end;
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A_RLWINM:
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begin
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{ convert srwi to rlwinm and see if the rlwinm }
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{ optimization can do something with it }
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taicpu(p).opcode := A_RLWINM;
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taicpu(p).ops := 5;
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taicpu(p).loadconst(3,taicpu(p).oper[2]^.val);
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taicpu(p).loadconst(4,31);
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taicpu(p).loadconst(2,(32-taicpu(p).oper[2]^.val) and 31);
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result := true;
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end;
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else
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internalerror(2019050941);
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end;
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end;
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A_RLWINM:
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begin
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if getnextinstruction(p,next1) and
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(next1.typ = ait_instruction) and
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((taicpu(next1).opcode = A_RLWINM) or
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(taicpu(next1).opcode = A_SRWI) or
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(taicpu(next1).opcode = A_SLWI)) and
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(taicpu(next1).oper[0]^.reg = taicpu(p).oper[0]^.reg) and
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// both source and target of next1 must equal target of p
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(taicpu(next1).oper[1]^.reg = taicpu(p).oper[0]^.reg) then
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begin
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case taicpu(next1).opcode of
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A_RLWINM:
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begin
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shlcount := taicpu(next1).oper[2]^.val;
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l2 := rlwinm2mask(taicpu(next1).oper[3]^.val,taicpu(next1).oper[4]^.val);
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end;
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A_SLWI:
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begin
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shlcount := taicpu(next1).oper[2]^.val;
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l2 := (-1) shl shlcount;
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end;
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A_SRWI:
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begin
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shlcount := 32-taicpu(next1).oper[2]^.val;
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l2 := (-1) shr taicpu(next1).oper[2]^.val;
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end;
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else
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internalerror(2013113008);
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end;
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l1 := rlwinm2mask((taicpu(p).oper[3]^.val-shlcount) and 31,(taicpu(p).oper[4]^.val-shlcount) and 31);
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l1 := l1 and l2;
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case l1 of
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-1:
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begin
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taicpu(p).oper[2]^.val := (taicpu(p).oper[2]^.val + shlcount) and 31;
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asml.remove(next1);
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next1.free;
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if (taicpu(p).oper[2]^.val = 0) then
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begin
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next1 := tai(p.next);
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asml.remove(p);
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p.free;
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p := next1;
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result := true;
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end;
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end;
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0:
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begin
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// masks have no bits in common
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taicpu(p).opcode := A_LI;
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taicpu(p).loadconst(1,0);
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taicpu(p).freeop(2);
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taicpu(p).freeop(3);
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taicpu(p).freeop(4);
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taicpu(p).ops := 2;
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taicpu(p).opercnt := 2;
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asml.remove(next1);
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next1.free;
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result := true;
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end
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else if tcgppc(cg).get_rlwi_const(l1,l1,l2) then
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begin
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taicpu(p).oper[2]^.val := (taicpu(p).oper[2]^.val + shlcount) and 31;
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taicpu(p).oper[3]^.val := l1;
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taicpu(p).oper[4]^.val := l2;
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asml.remove(next1);
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next1.free;
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result := true;
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end;
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end;
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end;
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end;
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else
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;
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end;
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end;
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else
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;
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end;
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end;
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const
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modifyflags: array[tasmop] of tasmop =
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(a_none, a_add_, a_add_, a_addo_, a_addo_, a_addc_, a_addc_, a_addco_, a_addco_,
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a_adde_, a_adde_, a_addeo_, a_addeo_, {a_addi could be addic_ if sure doesn't disturb carry} a_none, a_addic_, a_addic_, a_none,
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a_addme_, a_addme_, a_addmeo_, a_addmeo_, a_addze_, a_addze_, a_addzeo_,
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a_addzeo_, a_and_, a_and_, a_andc_, a_andc_, a_andi_, a_andis_, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_cntlzw_, a_cntlzw_, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_divw_, a_divw_, a_divwo_, a_divwo_,
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a_divwu_, a_divwu_, a_divwuo_, a_divwuo_, a_none, a_none, a_none, a_eqv_,
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a_eqv_, a_extsb_, a_extsb_, a_extsh_, a_extsh_, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_mffs, a_mffs_, a_mfmsr, a_mfspr, a_mfsr,
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a_mfsrin, a_mftb, a_mtcrf, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_mulhw_,
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a_mulhw_, a_mulhwu_, a_mulhwu_, a_none, a_mullw_, a_mullw_, a_mullwo_,
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a_mullwo_, a_nand_, a_nand_, a_neg_, a_neg_, a_nego_, a_nego_, a_nor_, a_nor_,
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a_or_, a_or_, a_orc_, a_orc_, a_none, a_none, a_none, a_rlwimi_, a_rlwimi_,
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a_rlwinm_, a_rlwinm_, a_rlwnm_, a_rlwnm_, a_none, a_slw_, a_slw_, a_sraw_, a_sraw_,
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a_srawi_, a_srawi_,a_srw_, a_srw_, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
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a_none, a_none, a_none, a_none, a_none, a_subf_, a_subf_, a_subfo_,
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a_subfo_, a_subfc_, a_subfc_, a_subfco_, a_subfco_, a_subfe_, a_subfe_,
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a_subfeo_, a_subfeo_, a_none, a_subfme_, a_subfme_, a_subfmeo_, a_subfmeo_,
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a_subfze_, a_subfze_, a_subfzeo_, a_subfzeo_, a_none, a_none, a_none,
|
|
a_none, a_none, a_none, a_xor_, a_xor_, a_none, a_none,
|
|
{ simplified mnemonics }
|
|
a_none, a_none, a_subic_, a_subic_, a_sub_, a_sub_, a_subo_, a_subo_,
|
|
a_subc_, a_subc_, a_subco_, a_subco_, a_none, a_none, a_none, a_none,
|
|
a_extlwi_, a_extlwi_, a_extrwi_, a_extrwi_, a_inslwi_, a_inslwi_, a_insrwi_,
|
|
a_insrwi_, a_rotlwi_, a_rotlwi_, a_rotlw_, a_rotlw_, a_slwi_, a_slwi_,
|
|
a_srwi_, a_srwi_, a_clrlwi_, a_clrlwi_, a_clrrwi_, a_clrrwi_, a_clrslwi_,
|
|
a_clrslwi_, a_none, a_none, a_none, a_none, a_none, a_none, a_none,
|
|
a_none, a_none {move to special purpose reg}, a_none {move from special purpose reg},
|
|
a_none, a_none, a_none, a_none, a_mr_, a_mr_, a_not_, a_not_, a_none, a_none, a_none,
|
|
a_none, a_none, a_none, a_none,
|
|
a_none, a_none, a_none, a_none, a_none);
|
|
|
|
function changetomodifyflags(p: taicpu): boolean;
|
|
begin
|
|
result := false;
|
|
if (modifyflags[p.opcode] <> a_none) then
|
|
begin
|
|
p.opcode := modifyflags[p.opcode];
|
|
result := true;
|
|
end;
|
|
end;
|
|
|
|
function TCpuAsmOptimizer.PostPeepHoleOptsCpu(var p: tai): boolean;
|
|
var
|
|
next1: tai;
|
|
begin
|
|
result := false;
|
|
case p.typ of
|
|
ait_instruction:
|
|
begin
|
|
case taicpu(p).opcode of
|
|
A_RLWINM_:
|
|
begin
|
|
// rlwinm_ is cracked on the G5, andi_/andis_ aren't
|
|
if (taicpu(p).oper[2]^.val = 0) then
|
|
if (taicpu(p).oper[3]^.val < 16) and
|
|
(taicpu(p).oper[4]^.val < 16) then
|
|
begin
|
|
taicpu(p).opcode := A_ANDIS_;
|
|
taicpu(p).oper[2]^.val := word(
|
|
((1 shl (16-taicpu(p).oper[3]^.val)) - 1) xor
|
|
((1 shl (15-taicpu(p).oper[4]^.val)) - 1));
|
|
taicpu(p).freeop(3);
|
|
taicpu(p).freeop(4);
|
|
taicpu(p).ops := 3;
|
|
taicpu(p).opercnt := 3;
|
|
end
|
|
else if (taicpu(p).oper[3]^.val >= 16) and
|
|
(taicpu(p).oper[4]^.val >= 16) then
|
|
begin
|
|
taicpu(p).opcode := A_ANDI_;
|
|
taicpu(p).oper[2]^.val := word(rlwinm2mask(taicpu(p).oper[3]^.val,taicpu(p).oper[4]^.val));
|
|
taicpu(p).freeop(3);
|
|
taicpu(p).freeop(4);
|
|
taicpu(p).ops := 3;
|
|
taicpu(p).opercnt := 3;
|
|
end;
|
|
end;
|
|
else
|
|
;
|
|
end;
|
|
|
|
// change "integer operation with destination reg" followed by a
|
|
// comparison to zero of that reg, with a variant of that integer
|
|
// operation which sets the flags (if it exists)
|
|
if not(result) and
|
|
(taicpu(p).ops >= 2) and
|
|
(taicpu(p).oper[0]^.typ = top_reg) and
|
|
(taicpu(p).oper[1]^.typ = top_reg) and
|
|
getnextinstruction(p,next1) and
|
|
(next1.typ = ait_instruction) and
|
|
(taicpu(next1).opcode = A_CMPWI) and
|
|
// make sure it the result goes to cr0
|
|
(((taicpu(next1).ops = 2) and
|
|
(taicpu(next1).oper[1]^.val = 0) and
|
|
(taicpu(next1).oper[0]^.reg = taicpu(p).oper[0]^.reg)) or
|
|
((taicpu(next1).ops = 3) and
|
|
(taicpu(next1).oper[2]^.val = 0) and
|
|
(taicpu(next1).oper[0]^.typ = top_reg) and
|
|
(getsupreg(taicpu(next1).oper[0]^.reg) = RS_CR0) and
|
|
(taicpu(next1).oper[1]^.reg = taicpu(p).oper[0]^.reg))) and
|
|
changetomodifyflags(taicpu(p)) then
|
|
begin
|
|
asml.remove(next1);
|
|
next1.free;
|
|
result := true;
|
|
end;
|
|
end;
|
|
else
|
|
;
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
casmoptimizer:=TCpuAsmOptimizer;
|
|
End.
|