wp_xxyyzz f0bada71d3 extrasyn: Add highlighters for JSON, Verilog, VHDL. Kindly provided by MRisco, issue #18248. Shorten menu in demo program. ... git-svn-id: https://svn.code.sf.net/p/lazarus-ccr/svn@8075 8e941d3f-bd1b-0410-a28a-d453659cc2b4		2021-08-18 21:27:43 +00:00
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lua.hgl	extrasyn: initial commit (additional synedit highlighters from https://bugs.freepascal.org/view.php?id=18248)	2018-03-04 09:33:24 +00:00
Mat Lab 6.hgl	extrasyn: initial commit (additional synedit highlighters from https://bugs.freepascal.org/view.php?id=18248)	2018-03-04 09:33:24 +00:00
Ruby.hgl	extrasyn: initial commit (additional synedit highlighters from https://bugs.freepascal.org/view.php?id=18248)	2018-03-04 09:33:24 +00:00
TestSynHighlighter.lpi	extrasyn: Add highlighters for JSON, Verilog, VHDL. Kindly provided by MRisco, issue #18248. Shorten menu in demo program.	2021-08-18 21:27:43 +00:00
TestSynHighlighter.lpr	extrasyn: initial commit (additional synedit highlighters from https://bugs.freepascal.org/view.php?id=18248)	2018-03-04 09:33:24 +00:00
unit1.lfm	extrasyn: Add highlighters for JSON, Verilog, VHDL. Kindly provided by MRisco, issue #18248. Shorten menu in demo program.	2021-08-18 21:27:43 +00:00
unit1.pas	extrasyn: Add highlighters for JSON, Verilog, VHDL. Kindly provided by MRisco, issue #18248. Shorten menu in demo program.	2021-08-18 21:27:43 +00:00