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https://gitlab.com/freepascal.org/lazarus/lazarus.git
synced 2025-08-29 05:50:21 +02:00
(cherry picked from commit 9cff61c5a0
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parent
07c3071d31
commit
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@ -3274,6 +3274,7 @@ begin
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then begin
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if flagVex in Flags
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then begin
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Exclude(Flags,flagModRM);
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if Vex.VectorLength = os128
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then SetOpcode(OPvzeroupper)
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else SetOpcode(OPvzeroall);
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@ -4351,7 +4352,7 @@ begin
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$A9: begin
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SetOpcode(OPtest);
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AddReg(regGeneral, OperandSize, REG_A);
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AddIv;
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AddIz;
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end;
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$AA: begin
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SetOpcode(OPstos, OPSx_b); CheckRepeat;
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@ -53,7 +53,7 @@ codeBytes, ' ', asmInstr,
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r := TRegExpr.Create('(\$)0+([0-9a-fA-F])');
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s := LowerCase(asmInstr);
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s := Trim(LowerCase(asmInstr));
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s := StringReplace(s, ' ', ' ', [rfReplaceAll]); // space
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s := StringReplace(s, ', ', ',', [rfReplaceAll]); // space
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s := r.Replace(s, '$1$2', True);
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@ -259,6 +259,11 @@ begin
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TestDis('vmovd [rax],xmm0', #$C4#$E1#$79#$7E#$00, 'vmovd [rax],xmm0');
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TestDis('vmovq [rax],xmm0', #$C4#$E1#$F9#$7E#$00, 'vmovq [rax],xmm0');
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TestDis('test rax,$FFFFFEFE', #$48#$A9#$FE#$FE#$FF#$FF, 'test rax,$FFFFFEFE');
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TestDis('test eax,$FFFFFEFE', #$A9#$FE#$FE#$FF#$FF, 'test eax,$FFFFFEFE');
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TestDis('vzeroupper', #$C5#$F8#$77, 'vzeroupper');
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TestDis('vzeroall', #$C5#$FC#$77, 'vzeroall');
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Process.NewMode := dm32;
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@ -373,6 +378,10 @@ begin
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TestDis('movd edi,xmm1', #$66#$0F#$7E#$CF, 'movd edi,xmm1');
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TestDis('vmovd [eax],xmm0', #$C4#$E1#$79#$7E#$00, 'vmovd [eax],xmm0');
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TestDis('test eax,$FFFFFEFE', #$A9#$FE#$FE#$FF#$FF, 'test eax,$FFFFFEFE');
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TestDis('vzeroupper', #$C5#$F8#$77, 'vzeroupper');
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TestDis('vzeroall', #$C5#$FC#$77, 'vzeroall');
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Process.NewMode := dm64;
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