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Added extra controller sub architectures for xtensa and riscv

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ccrause 2025-01-09 15:56:06 +02:00 committed by Maxim Ganetsky
parent 9eb9286e45
commit 7f2fd2fba8
1 changed files with 12 additions and 0 deletions
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12
components/codetools/definetemplates.pas
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@ -3997,6 +3997,8 @@ procedure GetTargetProcessors(const TargetCPU: string; aList: TStrings);
begin begin
aList.Add('lx106'); aList.Add('lx106');
aList.Add('lx6'); aList.Add('lx6');
aList.Add('lx7');
aList.Add('lx7hf');
end; end;
procedure LoongArch64; procedure LoongArch64;
@ -4007,6 +4009,16 @@ procedure GetTargetProcessors(const TargetCPU: string; aList: TStrings);
procedure Riscv32; procedure Riscv32;
begin begin
aList.Add('RISCV32'); aList.Add('RISCV32');
aList.Add('rv32imac');
aList.Add('rv32ima');
aList.Add('rv32im');
aList.Add('rv32i');
aList.Add('rv32e');
aList.Add('rv32imc');
aList.Add('rv32imafdc');
aList.Add('rv32imafd');
aList.Add('rv32ec');
aList.Add('rv32gc');
end; end;
procedure Riscv64; procedure Riscv64;