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Codetools: Add RISC-V selections to DefineTemplates. Issue #41067.

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This commit is contained in:
Juha 2024-08-19 14:53:32 +03:00
parent 85c17ebf3e
commit e751c618b6
1 changed files with 19 additions and 1 deletions
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20
components/codetools/definetemplates.pas
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@ -194,7 +194,7 @@ const
FPCOperatingSystemAlternative2Names: array[1..2] of shortstring =(
'bsd', 'linux' // see GetDefaultSrcOS2ForTargetOS
);
FPCProcessorNames: array[1..16] of shortstring =(
FPCProcessorNames: array[1..18] of shortstring =(
'aarch64',
'arm',
'avr',
@ -209,6 +209,8 @@ const
'powerpc64',
'sparc',
'x86_64',
'riscv32',
'riscv64',
'xtensa',
'wasm32'
);
@ -3852,6 +3854,10 @@ begin
Result:=Result+'ia64'
else if SysUtils.CompareText(TargetCPU,'aarch64')=0 then
Result:=Result+'aarch64'
else if SysUtils.CompareText(TargetCPU,'riscv32')=0 then
Result:=Result+'riscv32'
else if SysUtils.CompareText(TargetCPU,'riscv64')=0 then
Result:=Result+'riscv64'
else if SysUtils.CompareText(TargetCPU,'loongarch64')=0 then
Result:=Result+'loongarch64'
else if SysUtils.CompareText(TargetCPU,'xtensa')=0 then
@ -3998,6 +4004,16 @@ procedure GetTargetProcessors(const TargetCPU: string; aList: TStrings);
aList.Add('LOONGARCH64');
end;
procedure Riscv32;
begin
aList.Add('RISCV32');
end;
procedure Riscv64;
begin
aList.Add('RISCV64');
end;
begin
case TargetCPU of
'arm' : Arm;
@ -4012,6 +4028,8 @@ begin
'mipsel','mips' : Mips;
'jvm' : ;
'aarch64' : ;
'riscv32' : Riscv32;
'riscv64' : Riscv64;
'loongarch64' : LoongArch64;
'xtensa' : Xtensa;
'wasm32' : ;