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https://gitlab.com/freepascal.org/lazarus/lazarus.git
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871 lines
28 KiB
ObjectPascal
871 lines
28 KiB
ObjectPascal
{ $Id$ }
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{
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---------------------------------------------------------------------------
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fpdbgdisasavr.pp - Native Freepascal debugger - avr Disassembler
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---------------------------------------------------------------------------
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This unit contains an avr disassembler for the Native Freepascal debugger
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---------------------------------------------------------------------------
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@created(Mon Oct 18th 2019)
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@lastmod($Date$)
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@author()
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***************************************************************************
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* *
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* This source is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This code is distributed in the hope that it will be useful, but *
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* WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU *
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* General Public License for more details. *
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* *
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* A copy of the GNU General Public License is available on the World *
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* Wide Web at <http://www.gnu.org/copyleft/gpl.html>. You can also *
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* obtain it by writing to the Free Software Foundation, *
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* Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1335, USA. *
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* *
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***************************************************************************
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}
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unit FpDbgDisasAvr;
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{$mode objfpc}{$H+}
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interface
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uses
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SysUtils,
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FpDbgUtil, FpDbgInfo, DbgIntfBaseTypes, FpdMemoryTools, {$ifdef FORCE_LAZLOGGER_DUMMY} LazLoggerDummy {$else} LazLoggerBase {$endif},
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FpDbgClasses;
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type
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//The function Disassemble decodes the instruction at the given address.
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//Unrecognized instructions are assumed to be data statements [dw XXXX]
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TAvrAsmDecoder = class;
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{ TX86DisassemblerInstruction }
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{ TAvrAsmInstruction }
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TAvrAsmInstruction = class(TDbgAsmInstruction)
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private const
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INSTR_CODEBIN_LEN = 4;
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private
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FAsmDecoder: TAvrAsmDecoder;
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FAddress: TDBGPtr;
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FCodeBin: array[0..INSTR_CODEBIN_LEN-1] of byte;
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FFlags: set of (diCodeRead, diCodeReadError);
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protected
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procedure ReadCode; inline;
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public
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constructor Create(AAsmDecoder: TAvrAsmDecoder);
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procedure SetAddress(AnAddress: TDBGPtr);
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function IsCallInstruction: boolean; override;
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function IsReturnInstruction: boolean; override;
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function IsLeaveStackFrame: boolean; override;
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function InstructionLength: Integer; override;
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end;
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{ TAvrAsmDecoder }
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TAvrAsmDecoder = class(TDbgAsmDecoder)
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private
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FProcess: TDbgProcess;
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FLastErrWasMem: Boolean;
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FLastInstr: TAvrAsmInstruction;
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protected
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function GetLastErrorWasMemReadErr: Boolean; override;
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function GetMaxInstrSize: integer; override;
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function GetMinInstrSize: integer; override;
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function GetCanReverseDisassemble: boolean; override;
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public
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procedure Disassemble(var AAddress: Pointer; out ACodeBytes: String; out ACode: String); override;
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function GetInstructionInfo(AnAddress: TDBGPtr): TDbgAsmInstruction; override;
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// returns byte len of call instruction at AAddress // 0 if not a call intruction
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function GetFunctionFrameInfo(AnAddress: TDBGPtr; out
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AnIsOutsideFrame: Boolean): Boolean; override;
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constructor Create(AProcess: TDbgProcess); override;
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destructor Destroy;
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end;
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implementation
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uses
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StrUtils, LazClasses;
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const
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opRegReg = '%s r%d, r%d';
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opRegConst = '%s r%d, %d';
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opRegConstHex8 = '%s r%d, $%.2X';
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opRegConstHex16 = '%s r%d, $%.4X';
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opRegConstHex32 = '%s r%d, $%.8X';
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opConstReg = '%s %d, r%d';
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opConstHex8Reg = '%s $%.2X, r%d';
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opConstHex16Reg = '%s $%.4X, r%d';
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opConstHex32Reg = '%s $%.4X, r%d';
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opRegStr = '%s r%d, %s';
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opStrReg = '%s %s, r%d';
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opOnly = '%s';
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opStr = '%s %s';
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opConst = '%s %d';
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opConstHex8 = '%s $%.2X';
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opConstHex16 = '%s $%.4X';
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opConstHex8Const = '%s $%.2X, %d';
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opReg = '%s r%d';
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statusFlagNames: array[0..7] of char = ('c', 'z', 'n', 'v', 's', 'h', 't', 'i');
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branchIfSetNames: array[0..7] of string = ('brcs', 'breq', 'brmi', 'brvs', 'brlt', 'brhs', 'brts', 'brie');
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branchIfClrNames: array[0..7] of string = ('brcc', 'brne', 'brpl', 'brvc', 'brge', 'brhc', 'brtc', 'brid');
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procedure get_r_d_10(o: word; out r, d: byte);
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begin
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r := ((o shr 5) and $10) or (o and $f);
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d := (o shr 4) and $1f;
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end;
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procedure get_k_r16(o: word; out r, k: byte);
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begin
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r := 16 + ((o shr 4) and $f);
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k := byte((o and $0f00) shr 4) or (o and $f);
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end;
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// If non-valid opcode, assume it is a data statement
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function InvalidOpCode(instr: word): string;
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begin
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result := format(opConstHex16, ['dw', instr]);
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end;
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{ TAvrAsmInstruction }
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procedure TAvrAsmInstruction.ReadCode;
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begin
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if not (diCodeRead in FFlags) then begin
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if not FAsmDecoder.FProcess.ReadData(FAddress, INSTR_CODEBIN_LEN, FCodeBin) then
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Include(FFlags, diCodeReadError);
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Include(FFlags, diCodeRead);
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end;
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end;
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constructor TAvrAsmInstruction.Create(AAsmDecoder: TAvrAsmDecoder);
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begin
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FAsmDecoder := AAsmDecoder;
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inherited Create;
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AddReference;
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end;
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procedure TAvrAsmInstruction.SetAddress(AnAddress: TDBGPtr);
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begin
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FAddress := AnAddress;
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FFlags := [];
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end;
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function TAvrAsmInstruction.IsCallInstruction: boolean;
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var
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LoByte, HiByte: byte;
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begin
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Result := False;
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ReadCode;
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LoByte := FCodeBin[0];
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HiByte := FCodeBin[1];
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if ((HiByte and $FE) = $94) and ((LoByte and $0E) = $0E) or // call
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((HiByte = $95) and (LoByte in [$09, $19])) or // icall / eicall
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((HiByte and $D0) = $D0) then // rcall
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Result := true;
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end;
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function TAvrAsmInstruction.IsReturnInstruction: boolean;
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var
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LoByte, HiByte: byte;
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begin
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Result := False;
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ReadCode;
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LoByte := FCodeBin[0];
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HiByte := FCodeBin[1];
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if ((HiByte = $95) and (LoByte in [$08, $18])) then // ret / reti
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Result := true;
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end;
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function TAvrAsmInstruction.IsLeaveStackFrame: boolean;
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begin
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Result := false;
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end;
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function TAvrAsmInstruction.InstructionLength: Integer;
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var
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LoByte, HiByte: byte;
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begin
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Result := 2;
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ReadCode;
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LoByte := FCodeBin[0];
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HiByte := FCodeBin[1];
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if ((HiByte and $FE) = $94) and ((LoByte and $0E) in [$0C, $0E]) or // jmp / call
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((HiByte and $FE) in [$90, $92]) and ((LoByte and $0F) = $0) then // lds / sts
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Result := 4;
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end;
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function TAvrAsmDecoder.GetLastErrorWasMemReadErr: Boolean;
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begin
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Result := FLastErrWasMem;
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end;
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function TAvrAsmDecoder.GetMaxInstrSize: integer;
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begin
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Result := 4;
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end;
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function TAvrAsmDecoder.GetMinInstrSize: integer;
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begin
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Result := 2;
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end;
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function TAvrAsmDecoder.GetCanReverseDisassemble: boolean;
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begin
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Result := true;
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end;
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procedure TAvrAsmDecoder.Disassemble(var AAddress: Pointer; out
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ACodeBytes: String; out ACode: String);
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var
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CodeIdx, r, d, k, q: byte;
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a: SmallInt;
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pcode: PByte;
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code, addr16: word;
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s1: string;
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_set: boolean;
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begin
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pcode := AAddress;
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CodeIdx := 0;
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code := pcode[CodeIdx];
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inc(CodeIdx);
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code := code or (pcode[CodeIdx] shl 8);
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inc(CodeIdx);
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case (code and $f000) of
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$0000:
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begin
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case (code) of
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$0000: ACode := 'nop';
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else
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begin
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case (code and $fc00) of
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$0400:
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begin // CPC compare with carry 0000 01rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['cpc', d, r]);
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end;
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$0c00:
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begin // ADD without carry 0000 11 rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['add', d, r]);
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end;
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$0800:
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begin // SBC subtract with carry 0000 10rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['sbc', d, r]);
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end;
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else
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case (code and $ff00) of
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$0100:
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begin // MOVW – Copy Register Word 0000 0001 dddd rrrr
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d := ((code shr 4) and $f) shl 1;
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r := ((code) and $f) shl 1;
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ACode := format(opRegReg, ['movw', d, r]);
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end;
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$0200:
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begin // MULS – Multiply Signed 0000 0010 dddd rrrr
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r := 16 + (code and $f);
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d := 16 + ((code shr 4) and $f);
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ACode := format(opRegReg, ['muls', d, r]);
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end;
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$0300:
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begin // MUL Multiply 0000 0011 fddd frrr
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r := 16 + (code and $7);
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d := 16 + ((code shr 4) and $7);
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case (code and $88) of
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$00: ACode := format(opRegReg, ['mulsu', d, r]);
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$08: ACode := format(opRegReg, ['fmul', d, r]);
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$80: ACode := format(opRegReg, ['fmuls', d, r]);
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$88: ACode := format(opRegReg, ['fmulsu', d, r]);
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end;
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end;
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else
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ACode := InvalidOpCode(code);
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end;
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end;
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end;
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end;
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end;
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$1000:
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begin
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case (code and $fc00) of
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$1800:
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begin // SUB without carry 0000 10 rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['sub', d, r]);
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end;
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$1000:
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begin // CPSE Compare, skip if equal 0000 00 rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['cpse', d, r]);
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end;
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$1400:
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begin // CP Compare 0000 01 rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['cp', d, r]);
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end;
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$1c00:
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begin // ADD with carry 0001 11 rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['adc', d, r]);
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end;
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else
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ACode := InvalidOpCode(code);
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end;
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end;
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$2000:
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begin
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case (code and $fc00) of
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$2000:
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begin // AND 0010 00rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['and', d, r]);
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end;
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$2400:
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begin // EOR 0010 01rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['eor', d, r]);
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end;
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$2800:
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begin // OR Logical OR 0010 10rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['or', d, r]);
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end;
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$2c00:
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begin // MOV 0010 11rd dddd rrrr
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get_r_d_10(code, r, d);
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ACode := format(opRegReg, ['mov', d, r]);
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end;
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else
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ACode := InvalidOpCode(code);
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end;
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end;
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$3000:
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begin // CPI 0011 KKKK rrrr KKKK
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get_k_r16(code, d, k);
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ACode := format(opRegConstHex8, ['cpi', d, k]);
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end;
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$4000:
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begin // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
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get_k_r16(code, d, k);
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ACode := format(opRegConstHex8, ['sbci', d, k]);
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end;
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$5000:
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begin // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
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get_k_r16(code, d, k);
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ACode := format(opRegConstHex8, ['subi', d, k]);
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end;
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$6000:
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begin // ORI aka SBR Logical AND with Immediate 0110 kkkk dddd kkkk
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get_k_r16(code, d, k);
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ACode := format(opRegConstHex8, ['ori', d, k]);
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end;
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$7000:
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begin // ANDI Logical AND with Immediate 0111 kkkk dddd kkkk
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get_k_r16(code, d, k);
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ACode := format(opRegConstHex8, ['andi', d, k]);
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end;
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$a000,
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$8000:
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begin
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case (code and $d008) of
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$a000,
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$8000:
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begin // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
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d := (code shr 4) and $1f;
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q := ((code and $2000) shr 8) or ((code and $0c00) shr 7) or (code and $7);
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if (code and $0200) <> 0 then // store
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begin
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if q > 0 then
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ACode := format(opStrReg, ['std', 'Z+'+IntToStr(q), d])
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else
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begin
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case (code and 3) of
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0: s1 := 'Z';
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1: s1 := 'Z+';
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3: s1 := '-Z';
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end;
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ACode := format(opStrReg, ['st', s1, d]);
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end;
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end
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else // load
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begin
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if q > 0 then
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ACode := format(opRegStr, ['ldd', d, 'Z+'+IntToStr(q)])
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else
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begin
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case (code and 3) of
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0: s1 := 'Z';
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1: s1 := 'Z+';
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3: s1 := '-Z';
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end;
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ACode := format(opRegStr, ['ld', d, s1]);
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end;
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end;
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end;
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$a008,
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$8008:
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begin // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
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d := (code shr 4) and $1f;
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q := ((code and $2000) shr 8) or ((code and $0c00) shr 7) or (code and $7);
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if (code and $0200) <> 0 then // store
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begin
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if q > 0 then
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ACode := format(opStrReg, ['std', 'Y+'+IntToStr(q), d])
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else
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begin
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case (code and 3) of
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0: s1 := 'Y';
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1: s1 := 'Y+';
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3: s1 := '-Y';
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end;
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ACode := format(opStrReg, ['st', s1, d]);
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end;
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end
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else // load
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begin
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if q > 0 then
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ACode := format(opRegStr, ['ldd', d, 'Y+'+IntToStr(q)])
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else
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begin
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case (code and 3) of
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0: s1 := 'Y';
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1: s1 := 'Y+';
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3: s1 := '-Y';
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end;
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ACode := format(opRegStr, ['ld', d, s1]);
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end;
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end;
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end;
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else
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ACode := InvalidOpCode(code);
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end;
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end;
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$9000:
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begin
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if ((code and $ff0f) = $9408) then // clear/set SREG flags
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begin
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k := (code shr 4) and 7;
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if ((code and $0080) = 0) then
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s1 := 'se'
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else
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s1 := 'cl';
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ACode := format(opOnly, [s1 + statusFlagNames[k]]);
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end
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else
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case (code) of
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$9409: ACode := format(opOnly, ['ijmp']);
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$9419: ACode := format(opOnly, ['eijmp']);
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$9508: ACode := format(opOnly, ['ret']);
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$9509: ACode := format(opOnly, ['icall']);
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$9519: ACode := format(opOnly, ['eicall']);
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$9518: ACode := format(opOnly, ['reti']);
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$9588: ACode := format(opOnly, ['sleep']);
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$9598: ACode := format(opOnly, ['break']);
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$95a8: ACode := format(opOnly, ['wdr']);
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$95c8: ACode := format(opOnly, ['lpm']);
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$95d8: ACode := format(opOnly, ['elpm']);
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$95e8: ACode := format(opOnly, ['spm']);
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$95f8: ACode := format(opStr, ['spm', 'Z+']);
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$9408, $9418, $9428, $9438, $9448, $9458, $9468,
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$9478:
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begin // BSET 1001 0100 0ddd 1000
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d := (code shr 4) and 7;
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ACode := format(opConst, ['bset', d]);
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end;
|
||
$9488, $9498, $94a8, $94b8, $94c8, $94d8, $94e8,
|
||
$94f8: // bit 7 is 'clear vs set'
|
||
begin // BCLR 1001 0100 1ddd 1000
|
||
d := (code shr 4) and 7;
|
||
ACode := format(opConst, ['bclr', d]);
|
||
end;
|
||
else
|
||
begin
|
||
case (code and $fe0f) of
|
||
$9000:
|
||
begin // LDS Load Direct from fData Space, 32 bits
|
||
r := (code shr 4) and $1f;
|
||
addr16 := pcode[CodeIdx];
|
||
inc(CodeIdx);
|
||
addr16 := addr16 or (pcode[CodeIdx] shl 8);
|
||
inc(CodeIdx);
|
||
ACode := format(opRegConstHex16, ['lds', r, addr16]);
|
||
end;
|
||
$9005,
|
||
$9004:
|
||
begin // LPM Load Program Memory 1001 000d dddd 01oo
|
||
r := (code shr 4) and $1f;
|
||
if (code and 1 = 1) then
|
||
s1 := 'Z+'
|
||
else
|
||
s1 := 'Z';
|
||
ACode := format(opRegStr, ['lpm', r, s1]);
|
||
end;
|
||
$9006,
|
||
$9007:
|
||
begin // ELPM Extended Load Program Memory 1001 000d dddd 01oo
|
||
r := (code shr 4) and $1f;
|
||
if (code and 1 = 1) then
|
||
s1 := 'Z+'
|
||
else
|
||
s1 := 'Z';
|
||
ACode := format(opRegStr, ['elpm', r, s1]);
|
||
end;
|
||
$900c,
|
||
$900d,
|
||
$900e:
|
||
begin // LD Load Indirect from fData using X 1001 000r rrrr 11oo
|
||
r := (code shr 4) and $1f;
|
||
if (code and 3 = 1) then
|
||
s1 := 'X+'
|
||
else if (code and 3 = 2) then
|
||
s1 := '-X'
|
||
else
|
||
s1 := 'X';
|
||
ACode := format(opRegStr, ['ld', r, s1]);
|
||
end;
|
||
$920c,
|
||
$920d,
|
||
$920e:
|
||
begin // ST Store Indirect fData Space X 1001 001r rrrr 11oo
|
||
r := (code shr 4) and $1f;
|
||
if (code and 3 = 1) then
|
||
s1 := 'X+'
|
||
else if (code and 3 = 2) then
|
||
s1 := '-X'
|
||
else
|
||
s1 := 'X';
|
||
ACode := format(opStrReg, ['st', s1, r]);
|
||
end;
|
||
$9009,
|
||
$900a:
|
||
begin // LD Load Indirect from fData using Y 1001 000r rrrr 10oo
|
||
r := (code shr 4) and $1f;
|
||
if (code and 3 = 1) then
|
||
s1 := 'Y+'
|
||
else if (code and 3 = 2) then
|
||
s1 := '-Y';
|
||
ACode := format(opRegStr, ['ld', r, s1]);
|
||
end;
|
||
$9209,
|
||
$920a:
|
||
begin // ST Store Indirect fData Space Y 1001 001r rrrr 10oo
|
||
r := (code shr 4) and $1f;
|
||
if (code and 3 = 1) then
|
||
s1 := 'Y+'
|
||
else if (code and 3 = 2) then
|
||
s1 := '-Y';
|
||
ACode := format(opStrReg, ['st', s1, r]);
|
||
end;
|
||
$9200:
|
||
begin // STS Store Direct to Data Space, 32 bits
|
||
r := (code shr 4) and $1f;
|
||
addr16 := pcode[CodeIdx];
|
||
inc(CodeIdx);
|
||
addr16 := addr16 or (pcode[CodeIdx] shl 8);
|
||
inc(CodeIdx);
|
||
ACode := format(opConstHex16Reg, ['sts', addr16, r]);
|
||
end;
|
||
$9001,
|
||
$9002:
|
||
begin // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
|
||
r := (code shr 4) and $1f;
|
||
if (code and 3 = 1) then
|
||
s1 := 'Z+'
|
||
else
|
||
s1 := '-Z';
|
||
ACode := format(opRegStr, ['ld', r, s1]);
|
||
end;
|
||
$9201,
|
||
$9202:
|
||
begin // ST Store Indirect Data Space Z 1001 001r rrrr 0Xoo X=0 or XMega instructions X=1
|
||
r := (code shr 4) and $1f;
|
||
if (code and 4) = 0 then // normal AVR8 instruction
|
||
begin
|
||
if (code and 3 = 1) then
|
||
s1 := 'Z+'
|
||
else
|
||
s1 := '-Z';
|
||
ACode := format(opStrReg, ['st', s1, r]);
|
||
end
|
||
else
|
||
begin // AVR8X instructions
|
||
case (code and 3) of
|
||
0: s1 := 'xch';
|
||
1: s1 := 'las';
|
||
2: s1 := 'lac';
|
||
3: s1 := 'lat';
|
||
end;
|
||
ACode := format(opStrReg, [s1, 'Z', r]);
|
||
end;
|
||
end;
|
||
$900f:
|
||
begin // POP 1001 000d dddd 1111
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['pop', r]);
|
||
end;
|
||
$920f:
|
||
begin // PUSH 1001 001d dddd 1111
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['push', r]);
|
||
end;
|
||
$9400:
|
||
begin // COM – One’s Complement
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['com', r]);
|
||
end;
|
||
$9401:
|
||
begin // NEG – Two’s Complement
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['neg', r]);
|
||
end;
|
||
$9402:
|
||
begin // SWAP – Swap Nibbles
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['swap', r]);
|
||
end;
|
||
$9403:
|
||
begin // INC – Increment
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['inc', r]);
|
||
end;
|
||
$9405:
|
||
begin // ASR – Arithmetic Shift Right 1001 010d dddd 0101
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['asr', r]);
|
||
end;
|
||
$9406:
|
||
begin // LSR 1001 010d dddd 0110
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['lsr', r]);
|
||
end;
|
||
$9407:
|
||
begin // ROR 1001 010d dddd 0111
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['ror', r]);
|
||
end;
|
||
$940a:
|
||
begin // DEC – Decrement
|
||
r := (code shr 4) and $1f;
|
||
ACode := format(opReg, ['dec', r]);
|
||
end;
|
||
$940c,
|
||
$940d:
|
||
begin // JMP Long Call to sub, 32 bits
|
||
k := ((code and $01f0) shr 3) or (code and 1);
|
||
addr16 := pcode[CodeIdx];
|
||
inc(CodeIdx);
|
||
addr16 := addr16 or (pcode[CodeIdx] shl 8);
|
||
inc(CodeIdx);
|
||
ACode := format(opConstHex8, ['jmp', (dword(k shl 16) or dword(addr16)) shl 1]);
|
||
end;
|
||
$940e,
|
||
$940f:
|
||
begin // CALL Long Call to sub, 32 bits
|
||
k := ((code and $01f0) shr 3) or (code and 1);
|
||
addr16 := pcode[CodeIdx];
|
||
inc(CodeIdx);
|
||
addr16 := addr16 or (pcode[CodeIdx] shl 8);
|
||
inc(CodeIdx);
|
||
ACode := format(opConstHex8, ['call', (dword(k shl 16) or dword(addr16)) shl 1]);
|
||
end;
|
||
else
|
||
begin
|
||
case (code and $ff00) of
|
||
$9600:
|
||
begin // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
|
||
r := 24 + ((code shr 3) and $6);
|
||
k := ((code and $00c0) shr 2) or (code and $f);
|
||
ACode := format(opRegConstHex8, ['adiw', r, k]);
|
||
end;
|
||
$9700:
|
||
begin // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
|
||
r := 24 + ((code shr 3) and $6);
|
||
k := ((code and $00c0) shr 2) or (code and $f);
|
||
ACode := format(opRegConstHex8, ['sbiw', r, k]);
|
||
end;
|
||
$9800:
|
||
begin // CBI - Clear Bit in I/O Register 1001 1000 AAAA Abbb
|
||
d := (code shr 3) and $1f;
|
||
k := code and $7;
|
||
ACode := format(opConstHex8Const, ['cbi', d, k]);
|
||
end;
|
||
$9900:
|
||
begin // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
|
||
d := (code shr 3) and $1f;
|
||
k := code and $7;
|
||
ACode := format(opConstHex8Const, ['sbic', d, k]);
|
||
end;
|
||
$9a00:
|
||
begin // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
|
||
d := (code shr 3) and $1f;
|
||
k := code and $7;
|
||
ACode := format(opConstHex8Const, ['sbi', d, k]);
|
||
end;
|
||
$9b00:
|
||
begin // SBIS - Skip if Bit in I/O Register is Set 1001 1011 AAAA Abbb
|
||
d := (code shr 3) and $1f;
|
||
k := code and $7;
|
||
ACode := format(opConstHex8Const, ['sbis', d, k]);
|
||
end;
|
||
else
|
||
case (code and $fc00) of
|
||
$9c00:
|
||
begin // MUL - Multiply Unsigned 1001 11rd dddd rrrr
|
||
get_r_d_10(code, r, d);
|
||
ACode := format(opRegReg, ['mul', d, r]);
|
||
end;
|
||
else
|
||
ACode := InvalidOpCode(code);
|
||
end;
|
||
end;
|
||
end;
|
||
end;
|
||
end;
|
||
end;
|
||
end;
|
||
$b000:
|
||
begin
|
||
case (code and $f800) of
|
||
$b800:
|
||
begin // OUT A,Rr 1011 1AAr rrrr AAAA
|
||
r := (code shr 4) and $1f;
|
||
d := ((((code shr 9) and 3) shl 4) or ((code) and $f));
|
||
ACode := format(opConstHex8Reg, ['out', d, r]);
|
||
end;
|
||
$b000:
|
||
begin // IN Rd,A 1011 0AAr rrrr AAAA
|
||
r := (code shr 4) and $1f;
|
||
d := ((((code shr 9) and 3) shl 4) or ((code) and $f));
|
||
ACode := format(opRegConstHex8, ['in', r, d]);
|
||
end;
|
||
else
|
||
ACode := InvalidOpCode(code);
|
||
end;
|
||
end;
|
||
$c000:
|
||
begin // RJMP 1100 kkkk kkkk kkkk
|
||
a := smallint((word(code) shl 4) and $ffff) div 16;
|
||
ACode := format(opStr, ['rjmp', '.'+IntToStr(a shl 1)]);
|
||
end;
|
||
$d000:
|
||
begin // RCALL 1100 kkkk kkkk kkkk
|
||
a := smallint((word(code) shl 4) and $ffff) div 16;
|
||
ACode := format(opStr, ['rcall', '.'+IntToStr(a shl 1)]);
|
||
end;
|
||
$e000:
|
||
begin // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, $ff)
|
||
d := 16 + ((code shr 4) and $f);
|
||
k := ((code and $0f00) shr 4) or (code and $f);
|
||
ACode := format(opRegConstHex8, ['ldi', d, k]);
|
||
end;
|
||
$f000:
|
||
begin
|
||
case (code and $fe00) of
|
||
$f000,
|
||
$f200,
|
||
$f400,
|
||
$f600:
|
||
begin // All the fSREG branches
|
||
a := smallint(smallint(code shl 6) shr 9) * 2; // offset
|
||
k := code and 7;
|
||
_set := (code and $0400) = 0; // this bit means BRXC otherwise BRXS
|
||
if (_set) then
|
||
ACode := format(opStr, [branchIfSetNames[k], '.'+IntToStr(a)])
|
||
else
|
||
ACode := format(opStr, [branchIfClrNames[k], '.'+IntToStr(a)]);
|
||
end;
|
||
$f800,
|
||
$f900:
|
||
begin // BLD – Bit Load from T into a Bit in Register 1111 100r rrrr 0bbb
|
||
d := (code shr 4) and $1f; // register index
|
||
k := code and 7;
|
||
ACode := format(opRegConst, ['bld', d, k]);
|
||
end;
|
||
$fa00,
|
||
$fb00:
|
||
begin // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
|
||
r := (code shr 4) and $1f; // register index
|
||
k := code and 7;
|
||
ACode := format(opRegConst, ['bst', r, k]);
|
||
end;
|
||
$fc00,
|
||
$fe00:
|
||
begin // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
|
||
r := (code shr 4) and $1f; // register index
|
||
k := code and 7;
|
||
_set := (code and $0200) <> 0;
|
||
if _set then
|
||
ACode := format(opRegConst, ['sbrs', r, k])
|
||
else
|
||
ACode := format(opRegConst, ['sbrc', r, k]);
|
||
end;
|
||
else
|
||
ACode := InvalidOpCode(code);
|
||
end;
|
||
end;
|
||
else
|
||
ACode := InvalidOpCode(code);
|
||
end;
|
||
|
||
// memory
|
||
ACodeBytes := '';
|
||
for k := 0 to CodeIdx - 1 do
|
||
ACodeBytes := ACodeBytes + HexStr(pcode[k], 2);
|
||
|
||
Inc(AAddress, CodeIdx);
|
||
end;
|
||
|
||
function TAvrAsmDecoder.GetInstructionInfo(AnAddress: TDBGPtr
|
||
): TDbgAsmInstruction;
|
||
begin
|
||
if (FLastInstr = nil) or (FLastInstr.RefCount > 1) then begin
|
||
ReleaseRefAndNil(FLastInstr);
|
||
FLastInstr := TAvrAsmInstruction.Create(Self);
|
||
end;
|
||
|
||
FLastInstr.SetAddress(AnAddress);
|
||
Result := FLastInstr;
|
||
end;
|
||
|
||
function TAvrAsmDecoder.GetFunctionFrameInfo(AnAddress: TDBGPtr; out
|
||
AnIsOutsideFrame: Boolean): Boolean;
|
||
begin
|
||
result := false;
|
||
end;
|
||
|
||
constructor TAvrAsmDecoder.Create(AProcess: TDbgProcess);
|
||
begin
|
||
FProcess := AProcess;
|
||
end;
|
||
|
||
destructor TAvrAsmDecoder.Destroy;
|
||
begin
|
||
ReleaseRefAndNil(FLastInstr);
|
||
inherited Destroy;
|
||
end;
|
||
|
||
//var DBG_WARNINGS: PLazLoggerLogGroup;
|
||
initialization
|
||
//DBG_WARNINGS :=
|
||
DebugLogger.FindOrRegisterLogGroup('DBG_WARNINGS' {$IFDEF DBG_WARNINGS} , True {$ENDIF} );
|
||
|
||
end.
|