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Don't do ARM FoldShiftLdrStr peephole optimization if there's an offset in the reference.
Use UXTH+UXTB instructions instead of two shifts on processors that supports that. Eliminate internalerror when constant pointers are typecast as arrays. git-svn-id: trunk@26647 -
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@ -1376,7 +1376,8 @@ Implementation
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)
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)
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) and
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{ Only fold if there isn't another shifterop already. }
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{ Only fold if there isn't another shifterop already, and offset is zero. }
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(taicpu(hp1).oper[1]^.ref^.offset = 0) and
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(taicpu(hp1).oper[1]^.ref^.shiftmode = SM_None) and
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) and
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RegEndOfLife(taicpu(p).oper[0]^.reg, taicpu(hp1)) then
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@ -1022,7 +1022,15 @@ unit cgcpu;
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((lsb = 0) or ((lsb + width) = 32)) then
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begin
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shifterop_reset(so);
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if lsb = 0 then
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if (width = 16) and
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(lsb = 0) and
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(current_settings.cputype >= cpu_armv6) then
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list.concat(taicpu.op_reg_reg(A_UXTH,dst,src))
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else if (width = 8) and
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(lsb = 0) and
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(current_settings.cputype >= cpu_armv6) then
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list.concat(taicpu.op_reg_reg(A_UXTB,dst,src))
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else if lsb = 0 then
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begin
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so.shiftmode:=SM_LSL;
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so.shiftimm:=32-width;
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@ -378,6 +378,10 @@ interface
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if left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE] then
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location_freetemp(current_asmdata.CurrAsmList,left.location);
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end;
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LOC_CONSTANT:
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begin
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location.reference.offset:=left.location.value;
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end
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else
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internalerror(2002032216);
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end;
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