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* use 3 op cgobj methods when doing shl/shr code generation, this allows the cg to generate better code on risc archs having 3 operand shifts

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git-svn-id: trunk@14487 -
This commit is contained in:
florian 2009-12-27 20:19:23 +00:00
parent 1583907ac4
commit 0d57b2d8da
1 changed files with 7 additions and 6 deletions
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13
compiler/ncgmat.pas
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@ -239,7 +239,7 @@ implementation
location_copy(location,left.location);
location_force_reg(current_asmdata.CurrAsmList,location,OS_SINT,false);
cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NEG,OS_SINT,location.register,location.register);
if (cs_check_overflow in current_settings.localswitches) then
begin
current_asmdata.getjumplabel(hl);
@ -412,12 +412,13 @@ implementation
shrn: op:=OP_SHR;
end;
{ load left operators in a register }
location_copy(location,left.location);
if is_signed(left.resultdef) then
opsize:=OS_SINT
else
opsize:=OS_INT;
location_force_reg(current_asmdata.CurrAsmList,location,opsize,false);
location_force_reg(current_asmdata.CurrAsmList,left.location,opsize,true);
location_reset(location,LOC_REGISTER,opsize);
location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
{ shifting by a constant directly coded: }
if (right.nodetype=ordconstn) then
@ -425,8 +426,8 @@ implementation
{ l shl 32 should 0 imho, but neither TP nor Delphi do it in this way (FK)
if right.value<=31 then
}
cg.a_op_const_reg(current_asmdata.CurrAsmList,op,location.size,
tordconstnode(right).value.uvalue and 31,location.register);
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,location.size,
tordconstnode(right).value.uvalue and 31,left.location.register,location.register);
{
else
emit_reg_reg(A_XOR,S_L,hregister1,
@ -446,7 +447,7 @@ implementation
end
else
hcountreg:=right.location.register;
cg.a_op_reg_reg(current_asmdata.CurrAsmList,op,opsize,hcountreg,location.register);
cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,opsize,hcountreg,left.location.register,location.register);
end;
end;