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* correctly calculate the bit mask in thlcgobj.a_load_regconst_subsetreg_intern, resolves #31042
* convert immediates on x86 always to 32 (x86-64, i386) or 16 bit (i8086) signed values git-svn-id: trunk@35082 -
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@ -2384,11 +2384,18 @@ implementation
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if (slopt<>SL_REGNOSRCMASK) then
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a_op_const_reg(list,OP_AND,subsetregdef,tcgint(not(bitmask)),tmpreg);
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end;
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if (slopt<>SL_SETMAX) and
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{ the "and" is not needed if the whole register is modified (except for SL_SETZERO),
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because later on we do a move in this case instead of an or }
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((sreg.bitlen<>AIntBits) or (slopt=SL_SETZERO)) then
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a_op_const_reg(list,OP_AND,subsetregdef,tcgint(bitmask),sreg.subsetreg);
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begin
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{ shl could wrap around in this case }
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if subsetregdef.size=sizeof(aword) then
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a_op_const_reg(list,OP_AND,subsetregdef,tcgint(bitmask),sreg.subsetreg)
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else
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a_op_const_reg(list,OP_AND,subsetregdef,tcgint(bitmask) and aword((aword(1) shl (subsetregdef.size*8))-1),sreg.subsetreg);
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end;
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case slopt of
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SL_SETZERO : ;
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@ -1823,16 +1823,16 @@ unit cgx86;
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list.concat(taicpu.op_reg(A_DEC,TCgSize2OpSize[size],reg))
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end
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else
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list.concat(taicpu.op_const_reg(TOpCG2AsmOp[op],TCgSize2OpSize[size],aint(a),reg));
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list.concat(taicpu.op_const_reg(TOpCG2AsmOp[op],TCgSize2OpSize[size],ImmInt(a),reg));
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OP_AND,OP_OR:
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list.concat(taicpu.op_const_reg(TOpCG2AsmOp[op],TCgSize2OpSize[size],aint(a),reg));
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list.concat(taicpu.op_const_reg(TOpCG2AsmOp[op],TCgSize2OpSize[size],ImmInt(a),reg));
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OP_XOR:
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if (aword(a)=high(aword)) then
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list.concat(taicpu.op_reg(A_NOT,TCgSize2OpSize[size],reg))
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else
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list.concat(taicpu.op_const_reg(TOpCG2AsmOp[op],TCgSize2OpSize[size],aint(a),reg));
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list.concat(taicpu.op_const_reg(TOpCG2AsmOp[op],TCgSize2OpSize[size],ImmInt(a),reg));
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OP_SHL,OP_SHR,OP_SAR,OP_ROL,OP_ROR:
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begin
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@ -56,6 +56,12 @@ uses
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{ This should define the array of instructions as string }
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op2strtable=array[tasmop] of string[16];
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{$ifdef i8086}
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ImmInt = ShortInt;
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{$else i8086}
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ImmInt = Longint;
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{$endif i8086}
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const
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{ First value of opcode enumeration }
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firstop = low(tasmop);
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