mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-07 01:48:00 +02:00
+ support for the different flag registers of sparc
* fixing 64 bit cmp operations on sparc64 git-svn-id: trunk@36638 -
This commit is contained in:
florian
parent
4b30e5ee11
commit
28cfa838b5
@ -217,6 +217,9 @@ interface
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resflags.reg1:=NR_NO;
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resflags.reg2:=NR_NO;
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resflags.cond:=OC_NONE;
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{$elseif defined(sparcgen)}
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{ Load left node into flag F_NE/F_E }
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resflags.Init(NR_ICC,F_NE);
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{$else}
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{ Load left node into flag F_NE/F_E }
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resflags:=F_NE;
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@ -741,7 +741,7 @@ implementation
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list.concat(taicpu.op_reg_reg(A_MOV,NR_Y,tmpreg1));
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list.concat(taicpu.op_reg_reg(A_CMP,NR_G0,tmpreg1));
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ovloc.loc:=LOC_FLAGS;
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ovloc.resflags:=F_NE;
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ovloc.resflags.Init(NR_ICC,F_NE);
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end;
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OP_IMUL:
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begin
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@ -751,7 +751,7 @@ implementation
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list.concat(taicpu.op_reg_const_reg(A_SRA,dst,31,tmpreg2));
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list.concat(taicpu.op_reg_reg(A_CMP,tmpreg1,tmpreg2));
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ovloc.loc:=LOC_FLAGS;
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ovloc.resflags:=F_NE;
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ovloc.resflags.Init(NR_ICC,F_NE);
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end;
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end;
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end
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@ -776,7 +776,7 @@ implementation
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list.concat(taicpu.op_reg_reg(A_MOV,NR_Y,tmpreg1));
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list.concat(taicpu.op_reg_reg(A_CMP,NR_G0,tmpreg1));
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ovloc.loc:=LOC_FLAGS;
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ovloc.resflags:=F_NE;
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ovloc.resflags.Init(NR_ICC,F_NE);
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end;
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OP_IMUL:
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begin
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@ -786,7 +786,7 @@ implementation
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list.concat(taicpu.op_reg_const_reg(A_SRL,dst,31,tmpreg2));
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list.concat(taicpu.op_reg_reg(A_CMP,tmpreg1,tmpreg2));
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ovloc.loc:=LOC_FLAGS;
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ovloc.resflags:=F_NE;
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ovloc.resflags.Init(NR_ICC,F_NE);
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end;
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end;
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end
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@ -847,7 +847,18 @@ implementation
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var
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ai : taicpu;
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begin
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ai:=Taicpu.op_sym(A_Bxx,l);
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case f.FlagReg of
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{$ifdef SPARC64}
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NR_XCC:
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ai:=Taicpu.op_reg_sym(A_Bxx,f.FlagReg,l);
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{$endif SPARC64}
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NR_ICC:
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ai:=Taicpu.op_sym(A_Bxx,l);
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NR_FCC0:
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ai:=Taicpu.op_sym(A_FBxx,l);
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NR_FCC1,NR_FCC2,NR_FCC3:
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ai:=Taicpu.op_reg_sym(A_FBxx,f.FlagReg,l);
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end;
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ai.SetCondition(flags_to_cond(f));
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list.Concat(ai);
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{ Delay slot }
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@ -858,18 +869,31 @@ implementation
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procedure TCGSparcGen.g_flags2reg(list:TAsmList;Size:TCgSize;const f:tresflags;reg:TRegister);
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var
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hl : tasmlabel;
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ai : taicpu;
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begin
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if (f in [F_B]) then
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if (f.FlagReg=NR_ICC) and (f.Flags in [F_B]) then
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list.concat(taicpu.op_reg_reg_reg(A_ADDX,NR_G0,NR_G0,reg))
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else if (f in [F_AE]) then
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else if (f.FlagReg=NR_ICC) and (f.Flags in [F_AE]) then
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list.concat(taicpu.op_reg_const_reg(A_SUBX,NR_G0,-1,reg))
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else
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begin
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current_asmdata.getjumplabel(hl);
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a_load_const_reg(list,size,1,reg);
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a_jmp_flags(list,f,hl);
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a_load_const_reg(list,size,0,reg);
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a_label(list,hl);
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if current_settings.cputype in [cpu_SPARC_V9] then
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begin
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ai:=Taicpu.op_reg_const_reg(A_MOVcc,f.FlagReg,0,reg);
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ai.SetCondition(inverse_cond(flags_to_cond(f)));
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list.Concat(ai);
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ai:=Taicpu.op_reg_const_reg(A_MOVcc,f.FlagReg,1,reg);
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ai.SetCondition(flags_to_cond(f));
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list.Concat(ai);
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end
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else
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begin
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current_asmdata.getjumplabel(hl);
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a_load_const_reg(list,size,1,reg);
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a_jmp_flags(list,f,hl);
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a_load_const_reg(list,size,0,reg);
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a_label(list,hl);
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end;
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end;
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end;
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@ -23,6 +23,8 @@ unit cpubase;
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{$i fpcdefs.inc}
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{$ModeSwitch advancedrecords}
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interface
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uses
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@ -167,26 +169,32 @@ uses
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*****************************************************************************}
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type
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TResFlags=(
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{ Integer results }
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F_E, {Equal}
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F_NE, {Not Equal}
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F_G, {Greater}
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F_L, {Less}
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F_GE, {Greater or Equal}
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F_LE, {Less or Equal}
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F_A, {Above}
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F_AE, {Above or Equal, synonym: Carry Clear}
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F_B, {Below, synonym: Carry Set}
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F_BE, {Below or Equal}
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{ Floating point results }
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F_FE, {Equal}
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F_FNE, {Not Equal}
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F_FG, {Greater}
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F_FL, {Less}
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F_FGE, {Greater or Equal}
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F_FLE {Less or Equal}
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);
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TSparcFlags = (
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{ Integer results }
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F_E, {Equal}
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F_NE, {Not Equal}
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F_G, {Greater}
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F_L, {Less}
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F_GE, {Greater or Equal}
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F_LE, {Less or Equal}
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F_A, {Above}
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F_AE, {Above or Equal, synonym: Carry Clear}
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F_B, {Below, synonym: Carry Set}
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F_BE, {Below or Equal}
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{ Floating point results }
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F_FE, {Equal}
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F_FNE, {Not Equal}
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F_FG, {Greater}
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F_FL, {Less}
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F_FGE, {Greater or Equal}
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F_FLE {Less or Equal}
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);
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TResFlags = record
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{ either icc or xcc (64 bit }
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FlagReg : TRegister;
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Flags : TSparcFlags;
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procedure Init(r : TRegister;f : TSparcFlags);
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end;
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{*****************************************************************************
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Operand Sizes
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@ -212,8 +220,6 @@ uses
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fpuvarregs : Array [1..maxfpuvarregs] of TsuperRegister =
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(RS_F2);
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{*****************************************************************************
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Default generic sizes
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*****************************************************************************}
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@ -395,21 +401,21 @@ implementation
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procedure inverse_flags(var f: TResFlags);
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const
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inv_flags: array[TResFlags] of TResFlags =
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inv_flags: array[TSparcFlags] of TSparcFlags =
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(F_NE,F_E,F_LE,F_GE,F_L,F_G,F_BE,F_B,F_AE,F_A,
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F_FNE,F_FE,F_FLE,F_FGE,F_FL,F_FG);
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begin
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f:=inv_flags[f];
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f.Flags:=inv_flags[f.Flags];
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end;
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function flags_to_cond(const f:TResFlags):TAsmCond;
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const
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flags_2_cond:array[TResFlags] of TAsmCond=
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flags_2_cond:array[TSparcFlags] of TAsmCond=
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(C_E,C_NE,C_G,C_L,C_GE,C_LE,C_A,C_AE,C_B,C_BE,
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C_FE,C_FNE,C_FG,C_FL,C_FGE,C_FLE);
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begin
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result:=flags_2_cond[f];
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result:=flags_2_cond[f.Flags];
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end;
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@ -516,11 +522,13 @@ implementation
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result := inverse[c];
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end;
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function conditions_equal(const c1, c2: TAsmCond): boolean; {$ifdef USEINLINE}inline;{$endif USEINLINE}
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begin
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result := c1 = c2;
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end;
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function dwarf_reg(r:tregister):shortint;
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begin
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result:=regdwarf_table[findreg_by_number(r)];
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@ -528,4 +536,11 @@ implementation
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internalerror(200603251);
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end;
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procedure TResFlags.Init(r : TRegister; f : TSparcFlags);
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begin
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FlagReg:=r;
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Flags:=f;
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end;
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end.
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@ -31,7 +31,7 @@ interface
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type
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tsparcaddnode = class(tcgaddnode)
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private
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function GetResFlags(unsigned:Boolean):TResFlags;
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function GetResFlags(unsigned,use64bit:Boolean):TResFlags;
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function GetFPUResFlags:TResFlags;
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protected
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procedure second_addfloat;override;
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@ -63,39 +63,47 @@ interface
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TSparcAddNode
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*****************************************************************************}
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function TSparcAddNode.GetResFlags(unsigned:Boolean):TResFlags;
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function TSparcAddNode.GetResFlags(unsigned,use64bit:Boolean):TResFlags;
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var
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flagreg : TRegister;
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begin
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{$ifdef SPARC64}
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if use64bit then
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flagreg:=NR_XCC
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else
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{$endif SPARC64}
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flagreg:=NR_ICC;
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case NodeType of
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equaln:
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GetResFlags:=F_E;
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GetResFlags.Init(flagreg,F_E);
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unequaln:
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GetResFlags:=F_NE;
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GetResFlags.Init(flagreg,F_NE);
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else
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if not(unsigned) then
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begin
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if nf_swapped in flags then
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case NodeType of
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ltn:
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GetResFlags:=F_G;
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GetResFlags.Init(flagreg,F_G);
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lten:
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GetResFlags:=F_GE;
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GetResFlags.Init(flagreg,F_GE);
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gtn:
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GetResFlags:=F_L;
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GetResFlags.Init(flagreg,F_L);
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gten:
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GetResFlags:=F_LE;
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GetResFlags.Init(flagreg,F_LE);
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else
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internalerror(2014082010);
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_L;
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GetResFlags.Init(flagreg,F_L);
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lten:
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GetResFlags:=F_LE;
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GetResFlags.Init(flagreg,F_LE);
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gtn:
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GetResFlags:=F_G;
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GetResFlags.Init(flagreg,F_G);
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gten:
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GetResFlags:=F_GE;
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GetResFlags.Init(flagreg,F_GE);
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else
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internalerror(2014082011);
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end;
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@ -105,26 +113,26 @@ interface
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if nf_swapped in Flags then
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case NodeType of
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ltn:
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GetResFlags:=F_A;
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GetResFlags.Init(flagreg,F_A);
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lten:
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GetResFlags:=F_AE;
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GetResFlags.Init(flagreg,F_AE);
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gtn:
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GetResFlags:=F_B;
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GetResFlags.Init(flagreg,F_B);
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gten:
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GetResFlags:=F_BE;
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GetResFlags.Init(flagreg,F_BE);
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else
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internalerror(2014082012);
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end
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else
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case NodeType of
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ltn:
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GetResFlags:=F_B;
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GetResFlags.Init(flagreg,F_B);
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lten:
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GetResFlags:=F_BE;
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GetResFlags.Init(flagreg,F_BE);
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gtn:
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GetResFlags:=F_A;
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GetResFlags.Init(flagreg,F_A);
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gten:
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GetResFlags:=F_AE;
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GetResFlags.Init(flagreg,F_AE);
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else
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internalerror(2014082013);
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end;
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@ -137,34 +145,34 @@ interface
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begin
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case NodeType of
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equaln:
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result:=F_FE;
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result.Init(NR_FCC0,F_FE);
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unequaln:
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result:=F_FNE;
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result.Init(NR_FCC0,F_FNE);
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else
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begin
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if nf_swapped in Flags then
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case NodeType of
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ltn:
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result:=F_FG;
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result.Init(NR_FCC0,F_FG);
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lten:
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result:=F_FGE;
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result.Init(NR_FCC0,F_FGE);
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gtn:
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result:=F_FL;
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result.Init(NR_FCC0,F_FL);
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gten:
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result:=F_FLE;
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result.Init(NR_FCC0,F_FLE);
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else
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internalerror(2014082014);
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end
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else
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case NodeType of
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ltn:
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result:=F_FL;
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result.Init(NR_FCC0,F_FL);
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lten:
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result:=F_FLE;
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result.Init(NR_FCC0,F_FLE);
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gtn:
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result:=F_FG;
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result.Init(NR_FCC0,F_FG);
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gten:
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result:=F_FGE;
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result.Init(NR_FCC0,F_FGE);
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else
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internalerror(2014082015);
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end;
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@ -268,7 +276,7 @@ interface
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true);
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location.resflags:=getresflags(true,is_64bit(right.resultdef));
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end;
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@ -287,7 +295,7 @@ interface
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unequaln:
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0));
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location.resflags:=getresflags(true);
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location.resflags:=getresflags(true,is_64bit(right.resultdef));
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end;
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lten,
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gten:
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@ -300,7 +308,7 @@ interface
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,left.location.size);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_AND,left.location.register,right.location.register,tmpreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,tmpreg,right.location.register,NR_G0));
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location.resflags:=F_E;
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location.resflags.Init(NR_ICC,F_E);
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end;
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else
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internalerror(2012042701);
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@ -373,7 +381,7 @@ interface
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if (nodetype in [equaln,unequaln]) then
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begin
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location.resflags:=getresflags(unsigned);
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location.resflags:=getresflags(unsigned,false);
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if (right.location.loc=LOC_CONSTANT) then
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begin
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if hi(right.location.value64)<>0 then
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@ -417,13 +425,13 @@ interface
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if (nodetype in [ltn,gten]) then
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begin
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emit_compare(current_asmdata.CurrAsmList,left,right);
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location.resflags:=getresflags(unsigned);
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location.resflags:=getresflags(unsigned,false);
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end
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else if (nodetype in [lten,gtn]) then
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begin
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emit_compare(current_asmdata.CurrAsmList,right,left);
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toggleflag(nf_swapped);
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location.resflags:=getresflags(unsigned);
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location.resflags:=getresflags(unsigned,false);
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toggleflag(nf_swapped);
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end
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else
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@ -449,7 +457,7 @@ interface
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned);
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location.resflags:=getresflags(unsigned,is_64bit(right.resultdef));
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end;
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const
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@ -142,6 +142,7 @@ implementation
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href : treference;
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hregister : tregister;
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l1,l2 : tasmlabel;
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TempFlags : TResFlags;
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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@ -167,7 +168,8 @@ implementation
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(A_FiTOd,location.register,location.register));
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current_asmdata.CurrAsmList.concat(Taicpu.op_reg_reg(A_CMP,hregister,NR_G0));
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_GE,l2);
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TempFlags.Init(NR_ICC,F_GE);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,TempFlags,l2);
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case tfloatdef(resultdef).floattype of
|
||||
{ converting dword to s64real first and cut off at the end avoids precision loss }
|
||||
|
||||
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Reference in New Issue
Block a user