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Add Neg as a pseudo instruction, and fix RRX pseudo code expansion.

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Split some of the thumb code emission rules to make it easier to specify short-cut notations.

git-svn-id: branches/laksen/armiw@29345 -
This commit is contained in:
Jeppe Johansen 2014-12-27 17:44:30 +00:00
parent 6fff181679
commit 3ad03491ed
6 changed files with 224 additions and 75 deletions
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135
compiler/arm/aasmcpu.pas
View File

@ -1525,12 +1525,30 @@ implementation
SM_RRX: taicpu(curtai).opcode:=A_RRX; SM_RRX: taicpu(curtai).opcode:=A_RRX;
end; end;
if taicpu(curtai).oper[2]^.shifterop^.shiftmode=SM_RRX then
taicpu(curtai).ops:=2;
if taicpu(curtai).oper[2]^.shifterop^.rs=NR_NO then if taicpu(curtai).oper[2]^.shifterop^.rs=NR_NO then
taicpu(curtai).loadconst(2, taicpu(curtai).oper[2]^.shifterop^.shiftimm) taicpu(curtai).loadconst(2, taicpu(curtai).oper[2]^.shifterop^.shiftimm)
else else
taicpu(curtai).loadreg(2, taicpu(curtai).oper[2]^.shifterop^.rs); taicpu(curtai).loadreg(2, taicpu(curtai).oper[2]^.shifterop^.rs);
end; end;
end; end;
A_NEG:
begin
taicpu(curtai).opcode:=A_RSB;
if taicpu(curtai).ops=2 then
begin
taicpu(curtai).loadconst(2,0);
taicpu(curtai).ops:=3;
end
else
begin
taicpu(curtai).loadconst(1,0);
taicpu(curtai).ops:=2;
end;
end;
end; end;
end; end;
end; end;
@ -2258,7 +2276,7 @@ implementation
{ update condition flags { update condition flags
or floating point single } or floating point single }
if (oppostfix=PF_S) and if (oppostfix=PF_S) and
not(p^.code[0] in [#$04..#$0F,#$14..#$16,#$29,#$30, #$80..#$82]) then not(p^.code[0] in [#$04..#$0F,#$14..#$16,#$29,#$30,#$60..#$6B,#$80..#$82]) then
begin begin
Matches:=0; Matches:=0;
exit; exit;
@ -2278,7 +2296,7 @@ implementation
// ldr,str,ldrb,strb // ldr,str,ldrb,strb
#$17, #$17,
// stm,ldm // stm,ldm
#$26,#$8C, #$26,#$69,#$8C,
// vldm/vstm // vldm/vstm
#$44 #$44
]) then ]) then
@ -2304,7 +2322,8 @@ implementation
if p^.code[0] in [#$60..#$61] then if p^.code[0] in [#$60..#$61] then
begin begin
if (p^.code[0]=#$60) and if (p^.code[0]=#$60) and
(((not inIT) and (oppostfix<>PF_S)) or (GenerateThumb2Code and
((not inIT) and (oppostfix<>PF_S)) or
(inIT and (condition=C_None))) then (inIT and (condition=C_None))) then
begin begin
Matches:=0; Matches:=0;
@ -2319,7 +2338,8 @@ implementation
end end
else if p^.code[0]=#$62 then else if p^.code[0]=#$62 then
begin begin
if ((condition<>C_None) and if (GenerateThumb2Code and
(condition<>C_None) and
(not inIT) and (not inIT) and
(not lastinIT)) then (not lastinIT)) then
begin begin
@ -2339,9 +2359,9 @@ implementation
begin begin
if (opcode=A_MUL) then if (opcode=A_MUL) then
begin begin
if (ops<>3) or if (ops=3) and
(oper[2]^.typ<>top_reg) or ((oper[2]^.typ<>top_reg) or
(oper[0]^.reg<>oper[2]^.reg) then (oper[0]^.reg<>oper[2]^.reg)) then
begin begin
matches:=0; matches:=0;
exit; exit;
@ -4083,7 +4103,7 @@ implementation
else else
message(asmw_e_invalid_opcode_and_operands); message(asmw_e_invalid_opcode_and_operands);
end; end;
#$60..#$61: { Thumb } #$60: { Thumb }
begin begin
bytelen:=2; bytelen:=2;
bytes:=0; bytes:=0;
@ -4092,28 +4112,45 @@ implementation
bytes:=bytes or (ord(insentry^.code[1]) shl 8); bytes:=bytes or (ord(insentry^.code[1]) shl 8);
bytes:=bytes or ord(insentry^.code[2]); bytes:=bytes or ord(insentry^.code[2]);
{ set regs } { set regs }
if ops>=2 then if ops=2 then
begin begin
if oper[1]^.typ=top_reg then bytes:=bytes or (getsupreg(oper[0]^.reg) and $7);
begin bytes:=bytes or (getsupreg(oper[0]^.reg) shl 3);
bytes:=bytes or (getsupreg(oper[0]^.reg) and $7) or ((getsupreg(oper[0]^.reg) shr 3) shl 7); if (oper[1]^.typ=top_reg) then
bytes:=bytes or (getsupreg(oper[1]^.reg) shl 3); bytes:=bytes or ((getsupreg(oper[1]^.reg) and $7) shl 6)
else
if ops=3 then bytes:=bytes or ((oper[1]^.val and $1F) shl 6);
begin
case oper[2]^.typ of
top_const:
bytes:=bytes or ((oper[2]^.val and $1F) shl 6);
top_reg:
bytes:=bytes or ((getsupreg(oper[2]^.reg) and $7) shl 6);
end;
end;
end end
else if oper[1]^.typ=top_const then else if ops=3 then
begin begin
bytes:=bytes or ((getsupreg(oper[0]^.reg) and $7) shl 8); bytes:=bytes or (getsupreg(oper[0]^.reg) and $7);
bytes:=bytes or (oper[1]^.val and $FF); bytes:=bytes or (getsupreg(oper[1]^.reg) shl 3);
if (oper[2]^.typ=top_reg) then
bytes:=bytes or ((getsupreg(oper[2]^.reg) and $7) shl 6)
else
bytes:=bytes or ((oper[2]^.val and $1F) shl 6);
end
else if ops=1 then
begin
if oper[0]^.typ=top_const then
bytes:=bytes or (oper[0]^.val and $FF);
end; end;
end;
#$61: { Thumb }
begin
bytelen:=2;
bytes:=0;
{ set opcode }
bytes:=bytes or (ord(insentry^.code[1]) shl 8);
bytes:=bytes or ord(insentry^.code[2]);
{ set regs }
if ops=2 then
begin
bytes:=bytes or (getsupreg(oper[0]^.reg) and $7);
bytes:=bytes or ((getsupreg(oper[0]^.reg) and $8) shr 3) shl 7;
bytes:=bytes or (getsupreg(oper[1]^.reg) shl 3);
end end
else if ops=1 then else if ops=1 then
begin begin
@ -4167,12 +4204,20 @@ implementation
bytes:=bytes or (ord(insentry^.code[1]) shl 8); bytes:=bytes or (ord(insentry^.code[1]) shl 8);
bytes:=bytes or ord(insentry^.code[2]); bytes:=bytes or ord(insentry^.code[2]);
case opcode of case opcode of
A_SUB: A_SUB:
if(ops=3) then begin
bytes:=bytes or ((oper[2]^.val shr 2) and $7F); bytes:=bytes or (getsupreg(oper[0]^.reg) and $7);
if (ops=3) and
(oper[2]^.typ=top_const) then
bytes:=bytes or ((oper[2]^.val shr 2) and $7F)
else if (ops=2) and
(oper[1]^.typ=top_const) then
bytes:=bytes or ((oper[1]^.val shr 2) and $7F);
end;
A_MUL: A_MUL:
if (ops=3) then if (ops in [2,3]) then
begin begin
bytes:=bytes or (getsupreg(oper[0]^.reg) and $7); bytes:=bytes or (getsupreg(oper[0]^.reg) and $7);
bytes:=bytes or (getsupreg(oper[1]^.reg) shl 3); bytes:=bytes or (getsupreg(oper[1]^.reg) shl 3);
@ -4181,6 +4226,7 @@ implementation
begin begin
if ops=2 then if ops=2 then
begin begin
bytes:=bytes or (getsupreg(oper[0]^.reg) and $7);
bytes:=bytes or (getsupreg(oper[1]^.reg) shl $3); bytes:=bytes or (getsupreg(oper[1]^.reg) shl $3);
end end
else if (oper[0]^.reg<>NR_STACK_POINTER_REG) and else if (oper[0]^.reg<>NR_STACK_POINTER_REG) and
@ -4196,10 +4242,13 @@ implementation
bytes:=bytes or ((getsupreg(oper[0]^.reg) and $8) shr 3) shl 7; bytes:=bytes or ((getsupreg(oper[0]^.reg) and $8) shr 3) shl 7;
end end
else else
begin
bytes:=bytes or (getsupreg(oper[0]^.reg) and $7);
bytes:=bytes or ((oper[2]^.val shr 2) and $7F); bytes:=bytes or ((oper[2]^.val shr 2) and $7F);
end; end;
end; end;
end; end;
end;
#$65: { Thumb load/store } #$65: { Thumb load/store }
begin begin
bytelen:=2; bytelen:=2;
@ -4333,6 +4382,34 @@ implementation
bytes:=bytes or ((i_field and ord(insentry^.code[3])) xor (ord(insentry^.code[3]) shr 4)); bytes:=bytes or ((i_field and ord(insentry^.code[3])) xor (ord(insentry^.code[3]) shr 4));
end; end;
#$6B: { Thumb: Data processing (misc) }
begin
bytelen:=2;
bytes:=0;
{ set opcode }
bytes:=bytes or (ord(insentry^.code[1]) shl 8);
bytes:=bytes or ord(insentry^.code[2]);
{ set regs }
if ops>=2 then
begin
if oper[1]^.typ=top_const then
begin
bytes:=bytes or ((getsupreg(oper[0]^.reg) and $7) shl 8);
bytes:=bytes or (oper[1]^.val and $FF);
end
else if oper[1]^.typ=top_reg then
begin
bytes:=bytes or (getsupreg(oper[0]^.reg) and $7);
bytes:=bytes or (getsupreg(oper[1]^.reg) shl 3);
end;
end
else if ops=1 then
begin
if oper[0]^.typ=top_const then
bytes:=bytes or (oper[0]^.val and $FF);
end;
end;
#$80: { Thumb-2: Dataprocessing } #$80: { Thumb-2: Dataprocessing }
begin begin
bytes:=0; bytes:=0;

49
compiler/arm/armins.dat
View File

@ -86,7 +86,7 @@
void void none void void none
[ADCcc] [ADCcc]
reglo,reglo \x60\x41\x40 THUMB,ARMv4T reglo,reglo \x6B\x41\x40 THUMB,ARMv4T
reg32,immshifter \x80\xF1\x40\x0\x0 THUMB32,ARMv6T2 reg32,immshifter \x80\xF1\x40\x0\x0 THUMB32,ARMv6T2
reg32,reg32 \x80\xEB\x40\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEB\x40\x0\x0 THUMB32,WIDE,ARMv6T2
@ -103,8 +103,9 @@ reg32,reg32,immshifter \7\x2\xA0 ARM32,ARMv4
reg32,reg32 \x61\x44\x0 THUMB,ARMv4T reg32,reg32 \x61\x44\x0 THUMB,ARMv4T
reglo,reglo,reglo \x60\x18\x0 THUMB,ARMv4T reglo,reglo,reglo \x60\x18\x0 THUMB,ARMv4T
reglo,immshifter \x60\x1C\x0 THUMB,ARMv4T
reglo,reglo,immshifter \x60\x1C\x0 THUMB,ARMv4T reglo,reglo,immshifter \x60\x1C\x0 THUMB,ARMv4T
reglo,immshifter \x60\x30\x0 THUMB,ARMv4T reglo,immshifter \x6B\x30\x0 THUMB,ARMv4T
reglo,regsp,immshifter \x64\xA8\x00 THUMB,ARMv4T reglo,regsp,immshifter \x64\xA8\x00 THUMB,ARMv4T
regsp,regsp,immshifter \x64\xB0\x00 THUMB,ARMv4T regsp,regsp,immshifter \x64\xB0\x00 THUMB,ARMv4T
@ -140,7 +141,7 @@ reg32,memam2 \x81\xF2\xAF\x0\x0 THUMB32,WIDE,ARMv6T2
reg32,memam2 \x33\x2\x0F ARM32,ARMv4 reg32,memam2 \x33\x2\x0F ARM32,ARMv4
[ANDcc] [ANDcc]
reglo,reglo \x60\x40\x00 THUMB,ARMv4T reglo,reglo \x6B\x40\x00 THUMB,ARMv4T
reg32,immshifter \x80\xF0\x0\x0\x0 THUMB32,ARMv6T2 reg32,immshifter \x80\xF0\x0\x0\x0 THUMB32,ARMv6T2
reg32,reg32 \x80\xEA\x0\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEA\x0\x0\x0 THUMB32,WIDE,ARMv6T2
@ -166,7 +167,7 @@ imm24 \x1\x0A ARM32,ARMv4
mem32 \x1\x0A ARM32,ARMv4 mem32 \x1\x0A ARM32,ARMv4
[BICcc] [BICcc]
reglo,reglo \x60\x43\x80 THUMB,ARMv4T reglo,reglo \x6B\x43\x80 THUMB,ARMv4T
reg32,immshifter \x80\xF0\x20\x0\x0 THUMB32,ARMv6T2 reg32,immshifter \x80\xF0\x20\x0\x0 THUMB32,ARMv6T2
reg32,reg32 \x80\xEA\x20\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEA\x20\x0\x0 THUMB32,WIDE,ARMv6T2
@ -212,7 +213,7 @@ reg32 \3\x01\x2F\xFF\x10 ARM32,ARMv4T
reg8,reg8 \300\1\x10\101 ARM32,ARMv4 reg8,reg8 \300\1\x10\101 ARM32,ARMv4
[CMNcc] [CMNcc]
reglo,reglo \x60\x42\xC0 THUMB,ARMv4T reglo,reglo \x6B\x42\xC0 THUMB,ARMv4T
reg32,immshifter \x80\xF1\x10\x0F\x00 THUMB32,ARMv6T2 reg32,immshifter \x80\xF1\x10\x0F\x00 THUMB32,ARMv6T2
reg32,reg32 \x80\xEB\x10\x0F\x00 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEB\x10\x0F\x00 THUMB32,WIDE,ARMv6T2
@ -223,10 +224,10 @@ reg32,reg32,shifterop \xE\x1\x60 ARM32,ARMv4
reg32,immshifter \xF\x1\x60 ARM32,ARMv4 reg32,immshifter \xF\x1\x60 ARM32,ARMv4
[CMPcc] [CMPcc]
reglo,reglo \x60\x42\x80 THUMB,ARMv4T reglo,reglo \x6B\x42\x80 THUMB,ARMv4T
reg32,reg32 \x61\x45\x0 THUMB,ARMv4T reg32,reg32 \x61\x45\x0 THUMB,ARMv4T
reglo,immshifter \x60\x28\x0 THUMB,ARMv4T reglo,immshifter \x6B\x28\x0 THUMB,ARMv4T
reg32,immshifter \x80\xF1\xB0\x0F\x00 THUMB32,WIDE,ARMv6T2 reg32,immshifter \x80\xF1\xB0\x0F\x00 THUMB32,WIDE,ARMv6T2
reg32,reg32 \x80\xEB\xB0\x0F\x00 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEB\xB0\x0F\x00 THUMB32,WIDE,ARMv6T2
@ -256,7 +257,7 @@ reg32,reg32 \x32\x01\x6F\xF\x10 ARM32,ARMv4
[CPSIE] [CPSIE]
[EORcc] [EORcc]
reglo,reglo \x60\x40\x40 THUMB,ARMv4T reglo,reglo \x6B\x40\x40 THUMB,ARMv4T
reg32,immshifter \x80\xF0\x80\x0\x0 THUMB32,ARMv6T2 reg32,immshifter \x80\xF0\x80\x0\x0 THUMB32,ARMv6T2
reg32,reg32 \x80\xEA\x80\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEA\x80\x0\x0 THUMB32,WIDE,ARMv6T2
@ -357,10 +358,10 @@ reg32,reg32,reg32,reg32 \x80\xFB\x0\x0\x0 THUMB32,ARMv6T2
reg32,reg32,reg32,reg32 \x15\x00\x20\x9 ARM32,ARMv4 reg32,reg32,reg32,reg32 \x15\x00\x20\x9 ARM32,ARMv4
[MOVcc] [MOVcc]
reglo,reglo \x60\x0\x0 THUMB,ARMv4T reglo,reglo \x6B\x0\x0 THUMB,ARMv4T
reg32,reg32 \x61\x46\x00 THUMB,ARMv4T reg32,reg32 \x61\x46\x00 THUMB,ARMv4T
reglo,immshifter \x60\x20\x0 THUMB,ARMv4T reglo,immshifter \x6B\x20\x0 THUMB,ARMv4T
reg32,immshifter \x80\xF0\x4F\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,immshifter \x80\xF0\x4F\x0\x0 THUMB32,WIDE,ARMv6T2
@ -379,6 +380,7 @@ regf,immshifter \x13\x03\x28\xF0 ARM32,ARMv4
regs,immshifter \x13\x03\x28\xF0 ARM32,ARMv4 regs,immshifter \x13\x03\x28\xF0 ARM32,ARMv4
[MULcc] [MULcc]
reglo,reglo \x64\x43\x40 THUMB,ARMv4T
reglo,reglo,reglo \x64\x43\x40 THUMB,ARMv4T reglo,reglo,reglo \x64\x43\x40 THUMB,ARMv4T
reg32,reg32 \x80\xFB\x00\xF0\x00 THUMB32,ARMv6T2 reg32,reg32 \x80\xFB\x00\xF0\x00 THUMB32,ARMv6T2
reg32,reg32,reg32 \x80\xFB\x00\xF0\x00 THUMB32,ARMv6T2 reg32,reg32,reg32 \x80\xFB\x00\xF0\x00 THUMB32,ARMv6T2
@ -389,7 +391,7 @@ fpureg,fpureg \xF2 FPA
fpureg,immfpu \xF2 FPA fpureg,immfpu \xF2 FPA
[MVNcc] [MVNcc]
reglo,reglo \x60\x43\xc0 THUMB,ARMv4T reglo,reglo \x6B\x43\xc0 THUMB,ARMv4T
reg32,immshifter \x80\xF0\x6F\x0\x0 THUMB32,ARMv6T2 reg32,immshifter \x80\xF0\x6F\x0\x0 THUMB32,ARMv6T2
reg32,reg32 \x80\xEA\x6F\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEA\x6F\x0\x0 THUMB32,WIDE,ARMv6T2
@ -425,7 +427,7 @@ reg32,reg32,reg32 \x80\xEA\x60\x0\x0 THUMB32,ARMv6T2
reg32,reg32,reg32,shifterop \x80\xEA\x60\x0\x0 THUMB32,ARMv6T2 reg32,reg32,reg32,shifterop \x80\xEA\x60\x0\x0 THUMB32,ARMv6T2
[ORRcc] [ORRcc]
reglo,reglo \x60\x43\x00 THUMB,ARMv4T reglo,reglo \x6B\x43\x00 THUMB,ARMv4T
reg32,immshifter \x80\xF0\x40\x0\x0 THUMB32,ARMv6T2 reg32,immshifter \x80\xF0\x40\x0\x0 THUMB32,ARMv6T2
reg32,reg32 \x80\xEA\x40\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEA\x40\x0\x0 THUMB32,WIDE,ARMv6T2
@ -440,7 +442,7 @@ reg32,reg32,reg32,shifterop \6\x1\x80 ARM32,ARMv4
reg32,reg32,immshifter \7\x3\x80 ARM32,ARMv4 reg32,reg32,immshifter \7\x3\x80 ARM32,ARMv4
[RSBcc] [RSBcc]
reglo,reglo,immzero \x60\x42\x40 THUMB,ARMv4T reglo,reglo,immzero \x6B\x42\x40 THUMB,ARMv4T
reg32,immshifter \x80\xF1\xC0\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,immshifter \x80\xF1\xC0\x0\x0 THUMB32,WIDE,ARMv6T2
reg32,reg32 \x80\xEB\xC0\x0\x0 THUMB32,ARMv6T2 reg32,reg32 \x80\xEB\xC0\x0\x0 THUMB32,ARMv6T2
@ -460,7 +462,7 @@ reg32,reg32,reg32,shifterop \6\x0\xE0 ARM32,ARMv4
reg32,reg32,immshifter \7\x2\xE0 ARM32,ARMv4 reg32,reg32,immshifter \7\x2\xE0 ARM32,ARMv4
[SBCcc] [SBCcc]
reglo,reglo \x60\x41\x80 THUMB,ARMv4T reglo,reglo \x6B\x41\x80 THUMB,ARMv4T
reg32,immshifter \x80\xF1\x60\x0\x0 THUMB32,ARMv6T2 reg32,immshifter \x80\xF1\x60\x0\x0 THUMB32,ARMv6T2
reg32,reg32 \x80\xEB\x60\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEB\x60\x0\x0 THUMB32,WIDE,ARMv6T2
@ -527,11 +529,15 @@ reg32,memam2 \x88\xF8\x40\xE\x0\0 THUMB32,ARMv6T2
reg32,memam2 \x17\x04\x20 ARM32,ARMv4 reg32,memam2 \x17\x04\x20 ARM32,ARMv4
[SUBcc] [SUBcc]
regsp,immshifter \x64\xB0\x80 THUMB,ARMv4T
regsp,regsp,immshifter \x64\xB0\x80 THUMB,ARMv4T regsp,regsp,immshifter \x64\xB0\x80 THUMB,ARMv4T
reglo,reglo \x60\x1A\x0 THUMB,ARMv4T
reglo,reglo,reglo \x60\x1A\x0 THUMB,ARMv4T reglo,reglo,reglo \x60\x1A\x0 THUMB,ARMv4T
reglo,immshifter \x60\x1E\x0 THUMB,ARMv4T
reglo,reglo,immshifter \x60\x1E\x0 THUMB,ARMv4T reglo,reglo,immshifter \x60\x1E\x0 THUMB,ARMv4T
reglo,imm8 \x60\x38\x0 THUMB,ARMv4T reglo,imm8 \x6B\x38\x0 THUMB,ARMv4T
reglo,immshifter \x6B\x38\x0 THUMB,ARMv4T
reg32,immshifter \x80\xF1\xA0\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,immshifter \x80\xF1\xA0\x0\x0 THUMB32,WIDE,ARMv6T2
reg32,reg32 \x80\xEB\xA0\x0\x0 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEB\xA0\x0\x0 THUMB32,WIDE,ARMv6T2
@ -566,7 +572,7 @@ reg32,reg32,shifterop \xE\x1\x20 ARM32,ARMv4
reg32,immshifter \xF\x3\x20 ARM32,ARMv4 reg32,immshifter \xF\x3\x20 ARM32,ARMv4
[TSTcc] [TSTcc]
reglo,reglo \x60\x42\x00 THUMB,ARMv4T reglo,reglo \x6B\x42\x00 THUMB,ARMv4T
reg32,immshifter \x80\xF0\x10\x0F\x00 THUMB32,ARMv6T2 reg32,immshifter \x80\xF0\x10\x0F\x00 THUMB32,ARMv6T2
reg32,reg32 \x80\xEA\x10\x0F\x00 THUMB32,WIDE,ARMv6T2 reg32,reg32 \x80\xEA\x10\x0F\x00 THUMB32,WIDE,ARMv6T2
@ -850,8 +856,9 @@ void \x64\xBF\x40 THUMB,ARMv7
void \x2F\x3\x20\xF0\x4 ARM32,ARMv6K void \x2F\x3\x20\xF0\x4 ARM32,ARMv6K
[ASRcc] [ASRcc]
reglo,immshifter \x60\x1\x0 THUMB,ARMv4T
reglo,reglo,immshifter \x60\x1\x0 THUMB,ARMv4T reglo,reglo,immshifter \x60\x1\x0 THUMB,ARMv4T
reglo,reglo \x60\x41\x0 THUMB,ARMv4T reglo,reglo \x6B\x41\x0 THUMB,ARMv4T
reg32,immshifter \x82\xEA\x4F\x0\x20 THUMB32,WIDE,ARMv6T2 reg32,immshifter \x82\xEA\x4F\x0\x20 THUMB32,WIDE,ARMv6T2
reg32,reg32,immshifter \x82\xEA\x4F\x0\x20 THUMB32,WIDE,ARMv6T2 reg32,reg32,immshifter \x82\xEA\x4F\x0\x20 THUMB32,WIDE,ARMv6T2
@ -862,8 +869,9 @@ reg32,reg32,reg32 \x30\x1\xA0\x0\x50 ARM32,ARMv4
reg32,reg32,immshifter \x30\x1\xA0\x0\x40 ARM32,ARMv4 reg32,reg32,immshifter \x30\x1\xA0\x0\x40 ARM32,ARMv4
[LSRcc] [LSRcc]
reglo,immshifter \x60\x8\x0 THUMB,ARMv4T
reglo,reglo,immshifter \x60\x8\x0 THUMB,ARMv4T reglo,reglo,immshifter \x60\x8\x0 THUMB,ARMv4T
reglo,reglo \x60\x40\xC0 THUMB,ARMv4T reglo,reglo \x6B\x40\xC0 THUMB,ARMv4T
reg32,immshifter \x82\xEA\x4F\x0\x10 THUMB32,WIDE,ARMv6T2 reg32,immshifter \x82\xEA\x4F\x0\x10 THUMB32,WIDE,ARMv6T2
reg32,reg32,immshifter \x82\xEA\x4F\x0\x10 THUMB32,WIDE,ARMv6T2 reg32,reg32,immshifter \x82\xEA\x4F\x0\x10 THUMB32,WIDE,ARMv6T2
@ -874,8 +882,9 @@ reg32,reg32,reg32 \x30\x1\xA0\x0\x30 ARM32,ARMv4
reg32,reg32,immshifter \x30\x1\xA0\x0\x20 ARM32,ARMv4 reg32,reg32,immshifter \x30\x1\xA0\x0\x20 ARM32,ARMv4
[LSLcc] [LSLcc]
reglo,immshifter \x60\x0\x0 THUMB,ARMv4T
reglo,reglo,immshifter \x60\x0\x0 THUMB,ARMv4T reglo,reglo,immshifter \x60\x0\x0 THUMB,ARMv4T
reglo,reglo \x60\x40\x80 THUMB,ARMv4T reglo,reglo \x6B\x40\x80 THUMB,ARMv4T
reg32,immshifter \x82\xEA\x4F\x0\x00 THUMB32,WIDE,ARMv6T2 reg32,immshifter \x82\xEA\x4F\x0\x00 THUMB32,WIDE,ARMv6T2
reg32,reg32,immshifter \x82\xEA\x4F\x0\x00 THUMB32,WIDE,ARMv6T2 reg32,reg32,immshifter \x82\xEA\x4F\x0\x00 THUMB32,WIDE,ARMv6T2
@ -886,7 +895,7 @@ reg32,reg32,reg32 \x30\x1\xA0\x0\x10 ARM32,ARMv4
reg32,reg32,immshifter \x30\x1\xA0\x0\x00 ARM32,ARMv4 reg32,reg32,immshifter \x30\x1\xA0\x0\x00 ARM32,ARMv4
[RORcc] [RORcc]
reglo,reglo \x60\x41\xC0 THUMB,ARMv4T reglo,reglo \x6B\x41\xC0 THUMB,ARMv4T
reg32,immshifter \x82\xEA\x4F\x0\x30 THUMB32,WIDE,ARMv6T2 reg32,immshifter \x82\xEA\x4F\x0\x30 THUMB32,WIDE,ARMv6T2
reg32,reg32,immshifter \x82\xEA\x4F\x0\x30 THUMB32,WIDE,ARMv6T2 reg32,reg32,immshifter \x82\xEA\x4F\x0\x30 THUMB32,WIDE,ARMv6T2

2
compiler/arm/armnop.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from armins.dat } { don't edit, this file is generated from armins.dat }
694; 703;

103
compiler/arm/armtab.inc
View File

@ -11,7 +11,7 @@
opcode : A_ADC; opcode : A_ADC;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#65#64; code : #107#65#64;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -91,6 +91,13 @@
code : #96#24#0; code : #96#24#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
(
opcode : A_ADD;
ops : 2;
optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #96#28#0;
flags : if_thumb or if_armv4t
),
( (
opcode : A_ADD; opcode : A_ADD;
ops : 3; ops : 3;
@ -102,7 +109,7 @@
opcode : A_ADD; opcode : A_ADD;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #96#48#0; code : #107#48#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -249,7 +256,7 @@
opcode : A_AND; opcode : A_AND;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#64#0; code : #107#64#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -375,7 +382,7 @@
opcode : A_BIC; opcode : A_BIC;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#67#128; code : #107#67#128;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -571,7 +578,7 @@
opcode : A_CMN; opcode : A_CMN;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#66#192; code : #107#66#192;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -620,7 +627,7 @@
opcode : A_CMP; opcode : A_CMP;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#66#128; code : #107#66#128;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -634,7 +641,7 @@
opcode : A_CMP; opcode : A_CMP;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #96#40#0; code : #107#40#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -704,7 +711,7 @@
opcode : A_EOR; opcode : A_EOR;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#64#64; code : #107#64#64;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -1117,7 +1124,7 @@
opcode : A_MOV; opcode : A_MOV;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#0#0; code : #107#0#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -1131,7 +1138,7 @@
opcode : A_MOV; opcode : A_MOV;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #96#32#0; code : #107#32#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -1197,6 +1204,13 @@
code : #19#3#40#240; code : #19#3#40#240;
flags : if_arm32 or if_armv4 flags : if_arm32 or if_armv4
), ),
(
opcode : A_MUL;
ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #100#67#64;
flags : if_thumb or if_armv4t
),
( (
opcode : A_MUL; opcode : A_MUL;
ops : 3; ops : 3;
@ -1243,7 +1257,7 @@
opcode : A_MVN; opcode : A_MVN;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#67#192; code : #107#67#192;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -1397,7 +1411,7 @@
opcode : A_ORR; opcode : A_ORR;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#67#0; code : #107#67#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -1474,7 +1488,7 @@
opcode : A_RSB; opcode : A_RSB;
ops : 3; ops : 3;
optypes : (ot_reglo,ot_reglo,ot_immediatezero,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_immediatezero,ot_none,ot_none,ot_none);
code : #96#66#64; code : #107#66#64;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -1572,7 +1586,7 @@
opcode : A_SBC; opcode : A_SBC;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#65#128; code : #107#65#128;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -1855,6 +1869,13 @@
code : #23#4#32; code : #23#4#32;
flags : if_arm32 or if_armv4 flags : if_arm32 or if_armv4
), ),
(
opcode : A_SUB;
ops : 2;
optypes : (ot_regsp,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #100#176#128;
flags : if_thumb or if_armv4t
),
( (
opcode : A_SUB; opcode : A_SUB;
ops : 3; ops : 3;
@ -1862,6 +1883,13 @@
code : #100#176#128; code : #100#176#128;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
(
opcode : A_SUB;
ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#26#0;
flags : if_thumb or if_armv4t
),
( (
opcode : A_SUB; opcode : A_SUB;
ops : 3; ops : 3;
@ -1869,6 +1897,13 @@
code : #96#26#0; code : #96#26#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
(
opcode : A_SUB;
ops : 2;
optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #96#30#0;
flags : if_thumb or if_armv4t
),
( (
opcode : A_SUB; opcode : A_SUB;
ops : 3; ops : 3;
@ -1880,7 +1915,14 @@
opcode : A_SUB; opcode : A_SUB;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_immediate or ot_bits8,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_immediate or ot_bits8,ot_none,ot_none,ot_none,ot_none);
code : #96#56#0; code : #107#56#0;
flags : if_thumb or if_armv4t
),
(
opcode : A_SUB;
ops : 2;
optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #107#56#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -2034,7 +2076,7 @@
opcode : A_TST; opcode : A_TST;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#66#0; code : #107#66#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -2961,6 +3003,13 @@
code : #47#3#32#240#4; code : #47#3#32#240#4;
flags : if_arm32 or if_armv6k flags : if_arm32 or if_armv6k
), ),
(
opcode : A_ASR;
ops : 2;
optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #96#1#0;
flags : if_thumb or if_armv4t
),
( (
opcode : A_ASR; opcode : A_ASR;
ops : 3; ops : 3;
@ -2972,7 +3021,7 @@
opcode : A_ASR; opcode : A_ASR;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#65#0; code : #107#65#0;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -3017,6 +3066,13 @@
code : #48#1#160#0#64; code : #48#1#160#0#64;
flags : if_arm32 or if_armv4 flags : if_arm32 or if_armv4
), ),
(
opcode : A_LSR;
ops : 2;
optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #96#8#0;
flags : if_thumb or if_armv4t
),
( (
opcode : A_LSR; opcode : A_LSR;
ops : 3; ops : 3;
@ -3028,7 +3084,7 @@
opcode : A_LSR; opcode : A_LSR;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#64#192; code : #107#64#192;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -3073,6 +3129,13 @@
code : #48#1#160#0#32; code : #48#1#160#0#32;
flags : if_arm32 or if_armv4 flags : if_arm32 or if_armv4
), ),
(
opcode : A_LSL;
ops : 2;
optypes : (ot_reglo,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #96#0#0;
flags : if_thumb or if_armv4t
),
( (
opcode : A_LSL; opcode : A_LSL;
ops : 3; ops : 3;
@ -3084,7 +3147,7 @@
opcode : A_LSL; opcode : A_LSL;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#64#128; code : #107#64#128;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (
@ -3133,7 +3196,7 @@
opcode : A_ROR; opcode : A_ROR;
ops : 2; ops : 2;
optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none); optypes : (ot_reglo,ot_reglo,ot_none,ot_none,ot_none,ot_none);
code : #96#65#192; code : #107#65#192;
flags : if_thumb or if_armv4t flags : if_thumb or if_armv4t
), ),
( (

2
compiler/systems/i_embed.pas
View File

@ -61,7 +61,7 @@ unit i_embed;
Cprefix : ''; Cprefix : '';
newline : #10; newline : #10;
dirsep : '/'; dirsep : '/';
assem : as_gas; assem : as_arm_elf32;
assemextern : as_gas; assemextern : as_gas;
link : ld_none; link : ld_none;
linkextern : ld_embedded; linkextern : ld_embedded;

2
compiler/systems/i_linux.pas
View File

@ -650,7 +650,7 @@ unit i_linux;
dirsep : '/'; dirsep : '/';
assem : as_arm_elf32; assem : as_arm_elf32;
assemextern : as_gas; assemextern : as_gas;
link : ld_none; link : ld_int_linux;
linkextern : ld_linux; linkextern : ld_linux;
ar : ar_gnu_ar; ar : ar_gnu_ar;
res : res_elf; res : res_elf;