mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-21 18:09:30 +02:00
Add support for TBB/TBH instructions.
Precisize rules for selection of thumb instructions. Add short-cut notation support for most simple Thumb2 instructions ( add r1,#4 instead of add r1,r1,#4 ). git-svn-id: branches/laksen/armiw@29343 -
This commit is contained in:
Jeppe Johansen
parent
71cdedea82
commit
6fff181679
@ -2319,7 +2319,17 @@ implementation
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end
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else if p^.code[0]=#$62 then
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begin
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if (condition<>C_None) then
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if ((condition<>C_None) and
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(not inIT) and
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(not lastinIT)) then
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begin
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Matches:=0;
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exit;
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end;
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end
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else if p^.code[0]=#$63 then
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begin
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if inIT then
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begin
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Matches:=0;
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exit;
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@ -4370,6 +4380,7 @@ implementation
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else if ops=2 then
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begin
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bytes:=bytes or (getsupreg(oper[0]^.reg) shl 8);
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bytes:=bytes or (getsupreg(oper[0]^.reg) shl 16);
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if oper[1]^.typ=top_const then
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encodethumbimm(oper[1]^.val)
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@ -4470,7 +4481,10 @@ implementation
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bytes:=bytes or (getsupreg(oper[1]^.reg) shl 0);
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end
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else
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offset:=1;
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begin
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bytes:=bytes or (getsupreg(oper[0]^.reg) shl 0);
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offset:=1;
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end;
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if oper[offset]^.typ=top_const then
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begin
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@ -4887,6 +4901,28 @@ implementation
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bytes:=bytes or (((offset shr 22) xor (offset shr 23) xor 1) and $1) shl 13;
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bytes:=bytes or ((offset shr 23) and $1) shl 26;
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end;
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#$8E: { Thumb-2: TBB/TBH }
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begin
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{ set instruction code }
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bytes:=bytes or (ord(insentry^.code[1]) shl 24);
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bytes:=bytes or (ord(insentry^.code[2]) shl 16);
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bytes:=bytes or (ord(insentry^.code[3]) shl 8);
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bytes:=bytes or ord(insentry^.code[4]);
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{ set Rn and Rm }
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bytes:=bytes or getsupreg(oper[0]^.ref^.base) shl 16;
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if getregtype(oper[0]^.ref^.index)=R_INVALIDREGISTER then
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message(asmw_e_invalid_effective_address)
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else
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begin
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bytes:=bytes or getsupreg(oper[0]^.ref^.index);
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if (opcode=A_TBH) and
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(oper[0]^.ref^.shiftmode<>SM_LSL) and
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(oper[0]^.ref^.shiftimm<>1) then
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message(asmw_e_invalid_effective_address);
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end;
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end;
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#$fe: // No written data
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begin
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exit;
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@ -88,6 +88,9 @@ void void none
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[ADCcc]
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reglo,reglo \x60\x41\x40 THUMB,ARMv4T
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reg32,immshifter \x80\xF1\x40\x0\x0 THUMB32,ARMv6T2
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reg32,reg32 \x80\xEB\x40\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,shifterop \x80\xEB\x40\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x80\xF1\x40\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32 \x80\xEB\x40\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEB\x40\x0\x0 THUMB32,WIDE,ARMv6T2
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@ -108,6 +111,9 @@ regsp,regsp,immshifter \x64\xB0\x00 THUMB,ARMv4T
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reg32,regsp,reg32 \x64\x44\x68 THUMB,ARMv4T
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regsp,reg32 \x64\x44\x85 THUMB,ARMv4T
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reg32,immshifter \x80\xF1\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32 \x80\xEB\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,shifterop \x80\xEB\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x80\xF1\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x80\xEB\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEB\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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@ -136,6 +142,9 @@ reg32,memam2 \x33\x2\x0F ARM32,ARMv4
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[ANDcc]
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reglo,reglo \x60\x40\x00 THUMB,ARMv4T
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reg32,immshifter \x80\xF0\x0\x0\x0 THUMB32,ARMv6T2
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reg32,reg32 \x80\xEA\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,shifterop \x80\xEA\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x80\xF0\x0\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32 \x80\xEA\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEA\x0\x0\x0 THUMB32,WIDE,ARMv6T2
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@ -159,6 +168,9 @@ mem32 \x1\x0A ARM32,ARMv4
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[BICcc]
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reglo,reglo \x60\x43\x80 THUMB,ARMv4T
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reg32,immshifter \x80\xF0\x20\x0\x0 THUMB32,ARMv6T2
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reg32,reg32 \x80\xEA\x20\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,shifterop \x80\xEA\x20\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x80\xF0\x20\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32 \x80\xEA\x20\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEA\x20\x0\x0 THUMB32,WIDE,ARMv6T2
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@ -246,6 +258,9 @@ reg32,reg32 \x32\x01\x6F\xF\x10 ARM32,ARMv4
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[EORcc]
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reglo,reglo \x60\x40\x40 THUMB,ARMv4T
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reg32,immshifter \x80\xF0\x80\x0\x0 THUMB32,ARMv6T2
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reg32,reg32 \x80\xEA\x80\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,shifterop \x80\xEA\x80\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x80\xF0\x80\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32 \x80\xEA\x80\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEA\x80\x0\x0 THUMB32,WIDE,ARMv6T2
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@ -365,6 +380,7 @@ regs,immshifter \x13\x03\x28\xF0 ARM32,ARMv4
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[MULcc]
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reglo,reglo,reglo \x64\x43\x40 THUMB,ARMv4T
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reg32,reg32 \x80\xFB\x00\xF0\x00 THUMB32,ARMv6T2
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reg32,reg32,reg32 \x80\xFB\x00\xF0\x00 THUMB32,ARMv6T2
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reg32,reg32,reg32 \x14\x00\x00\x90 ARM32,ARMv4
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@ -401,13 +417,19 @@ void \x2F\x03\x20\xF0\x0 ARM32,ARMv6K
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void \x2F\xE1\xA0\x0\x0 ARM32,ARMv4
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[ORNcc]
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reg32,immshifter \x80\xF0\x60\x0\x0 THUMB32,ARMv6T2
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reg32,reg32 \x80\xEA\x60\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,shifterop \x80\xEA\x60\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,immshifter \x80\xF0\x60\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32 \x80\xEA\x60\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEA\x60\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x80\xEA\x60\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEA\x60\x0\x0 THUMB32,ARMv6T2
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[ORRcc]
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reglo,reglo \x60\x43\x00 THUMB,ARMv4T
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reg32,immshifter \x80\xF0\x40\x0\x0 THUMB32,ARMv6T2
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reg32,reg32 \x80\xEA\x40\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,shifterop \x80\xEA\x40\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x80\xF0\x40\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32 \x80\xEA\x40\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEA\x40\x0\x0 THUMB32,WIDE,ARMv6T2
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@ -420,9 +442,12 @@ reg32,reg32,immshifter \7\x3\x80 ARM32,ARMv4
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[RSBcc]
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reglo,reglo,immzero \x60\x42\x40 THUMB,ARMv4T
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reg32,immshifter \x80\xF1\xC0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32 \x80\xEB\xC0\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,shifterop \x80\xEB\xC0\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,immshifter \x80\xF1\xC0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x80\xEB\xC0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEB\xC0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x80\xEB\xC0\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEB\xC0\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32 \6\x0\x60 ARM32,ARMv4
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reg32,reg32,reg32,shifterop \6\x0\x60 ARM32,ARMv4
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@ -437,7 +462,10 @@ reg32,reg32,immshifter \7\x2\xE0 ARM32,ARMv4
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[SBCcc]
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reglo,reglo \x60\x41\x80 THUMB,ARMv4T
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reg32,reg32,immshifter \x80\xF1\x60\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,immshifter \x80\xF1\x60\x0\x0 THUMB32,ARMv6T2
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reg32,reg32 \x80\xEB\x60\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,shifterop \x80\xEB\x60\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x80\xF1\x60\x0\x0 THUMB32,ARMv6T2
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reg32,reg32,reg32 \x80\xEB\x60\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEB\x60\x0\x0 THUMB32,WIDE,ARMv6T2
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@ -505,6 +533,9 @@ reglo,reglo,reglo \x60\x1A\x0 THUMB,ARMv4T
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reglo,reglo,immshifter \x60\x1E\x0 THUMB,ARMv4T
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reglo,imm8 \x60\x38\x0 THUMB,ARMv4T
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reg32,immshifter \x80\xF1\xA0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32 \x80\xEB\xA0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,shifterop \x80\xEB\xA0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x80\xF1\xA0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x80\xEB\xA0\x0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32,shifterop \x80\xEB\xA0\x0\x0 THUMB32,WIDE,ARMv6T2
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@ -822,7 +853,9 @@ void \x2F\x3\x20\xF0\x4 ARM32,ARMv6K
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reglo,reglo,immshifter \x60\x1\x0 THUMB,ARMv4T
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reglo,reglo \x60\x41\x0 THUMB,ARMv4T
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reg32,immshifter \x82\xEA\x4F\x0\x20 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x82\xEA\x4F\x0\x20 THUMB32,WIDE,ARMv6T2
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reg32,reg32 \x80\xFA\x40\xF0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x80\xFA\x40\xF0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x30\x1\xA0\x0\x50 ARM32,ARMv4
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@ -832,7 +865,9 @@ reg32,reg32,immshifter \x30\x1\xA0\x0\x40 ARM32,ARMv4
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reglo,reglo,immshifter \x60\x8\x0 THUMB,ARMv4T
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reglo,reglo \x60\x40\xC0 THUMB,ARMv4T
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reg32,immshifter \x82\xEA\x4F\x0\x10 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x82\xEA\x4F\x0\x10 THUMB32,WIDE,ARMv6T2
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reg32,reg32 \x80\xFA\x20\xF0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x80\xFA\x20\xF0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x30\x1\xA0\x0\x30 ARM32,ARMv4
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@ -842,7 +877,9 @@ reg32,reg32,immshifter \x30\x1\xA0\x0\x20 ARM32,ARMv4
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reglo,reglo,immshifter \x60\x0\x0 THUMB,ARMv4T
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reglo,reglo \x60\x40\x80 THUMB,ARMv4T
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reg32,immshifter \x82\xEA\x4F\x0\x00 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x82\xEA\x4F\x0\x00 THUMB32,WIDE,ARMv6T2
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reg32,reg32 \x80\xFA\x60\xF0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x80\xFA\x60\xF0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x30\x1\xA0\x0\x10 ARM32,ARMv4
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@ -851,7 +888,9 @@ reg32,reg32,immshifter \x30\x1\xA0\x0\x00 ARM32,ARMv4
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[RORcc]
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reglo,reglo \x60\x41\xC0 THUMB,ARMv4T
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reg32,immshifter \x82\xEA\x4F\x0\x30 THUMB32,WIDE,ARMv6T2
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reg32,reg32,immshifter \x82\xEA\x4F\x0\x30 THUMB32,WIDE,ARMv6T2
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reg32,reg32 \x80\xFA\x60\xF0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x80\xFA\x60\xF0\x0 THUMB32,WIDE,ARMv6T2
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reg32,reg32,reg32 \x30\x1\xA0\x0\x70 ARM32,ARMv4
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@ -1354,8 +1393,11 @@ condition \xFE ARM32,ARMv4
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condition \x6A\xBF\x01\x0E THUMB,ARMv6T2
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condition \xFE ARM32,ARMv4
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[TBB]
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[TBH]
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[TBBcc]
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memam2 \x8E\xE8\xD0\xF0\x00 THUMB32,ARMv6T2
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[TBHcc]
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memam2 \x8E\xE8\xD0\xF0\x10 THUMB32,ARMv6T2
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[MOVW]
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reg32,imm32 \x2C\x3\x0 ARM32,ARMv6T2
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@ -1,2 +1,2 @@
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{ don't edit, this file is generated from armins.dat }
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653;
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694;
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@ -14,6 +14,27 @@
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code : #96#65#64;
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flags : if_thumb or if_armv4t
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),
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(
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opcode : A_ADC;
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ops : 2;
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optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
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code : #128#241#64#0#0;
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flags : if_thumb32 or if_armv6t2
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),
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(
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opcode : A_ADC;
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ops : 2;
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optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
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code : #128#235#64#0#0;
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flags : if_thumb32 or if_wide or if_armv6t2
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),
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(
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opcode : A_ADC;
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ops : 3;
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optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
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code : #128#235#64#0#0;
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flags : if_thumb32 or if_wide or if_armv6t2
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),
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(
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opcode : A_ADC;
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ops : 3;
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@ -112,6 +133,27 @@
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code : #100#68#133;
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flags : if_thumb or if_armv4t
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),
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(
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opcode : A_ADD;
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ops : 2;
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optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
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code : #128#241#0#0#0;
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flags : if_thumb32 or if_wide or if_armv6t2
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),
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(
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opcode : A_ADD;
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ops : 2;
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optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
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code : #128#235#0#0#0;
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flags : if_thumb32 or if_wide or if_armv6t2
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),
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(
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opcode : A_ADD;
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ops : 3;
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optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
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code : #128#235#0#0#0;
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flags : if_thumb32 or if_wide or if_armv6t2
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),
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(
|
||||
opcode : A_ADD;
|
||||
ops : 3;
|
||||
@ -210,6 +252,27 @@
|
||||
code : #96#64#0;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_AND;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#240#0#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_AND;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#234#0#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_AND;
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
|
||||
code : #128#234#0#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_AND;
|
||||
ops : 3;
|
||||
@ -315,6 +378,27 @@
|
||||
code : #96#67#128;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_BIC;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#240#32#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_BIC;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#234#32#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_BIC;
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
|
||||
code : #128#234#32#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_BIC;
|
||||
ops : 3;
|
||||
@ -623,6 +707,27 @@
|
||||
code : #96#64#64;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_EOR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#240#128#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_EOR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#234#128#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_EOR;
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
|
||||
code : #128#234#128#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_EOR;
|
||||
ops : 3;
|
||||
@ -1099,6 +1204,13 @@
|
||||
code : #100#67#64;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_MUL;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#251#0#240#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_MUL;
|
||||
ops : 3;
|
||||
@ -1239,6 +1351,27 @@
|
||||
code : #47#225#160#0#0;
|
||||
flags : if_arm32 or if_armv4
|
||||
),
|
||||
(
|
||||
opcode : A_ORN;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#240#96#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ORN;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#234#96#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ORN;
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
|
||||
code : #128#234#96#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ORN;
|
||||
ops : 3;
|
||||
@ -1251,14 +1384,14 @@
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
|
||||
code : #128#234#96#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ORN;
|
||||
ops : 4;
|
||||
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
|
||||
code : #128#234#96#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ORR;
|
||||
@ -1267,6 +1400,27 @@
|
||||
code : #96#67#0;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_ORR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#240#64#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ORR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#234#64#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ORR;
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
|
||||
code : #128#234#64#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ORR;
|
||||
ops : 3;
|
||||
@ -1323,6 +1477,27 @@
|
||||
code : #96#66#64;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_RSB;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#241#192#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_RSB;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#235#192#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_RSB;
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
|
||||
code : #128#235#192#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_RSB;
|
||||
ops : 3;
|
||||
@ -1335,14 +1510,14 @@
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_none,ot_none,ot_none);
|
||||
code : #128#235#192#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_RSB;
|
||||
ops : 4;
|
||||
optypes : (ot_reg32,ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none);
|
||||
code : #128#235#192#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_RSB;
|
||||
@ -1400,12 +1575,33 @@
|
||||
code : #96#65#128;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_SBC;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#241#96#0#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_SBC;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#235#96#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_SBC;
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
|
||||
code : #128#235#96#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_SBC;
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none);
|
||||
code : #128#241#96#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_SBC;
|
||||
@ -1687,6 +1883,27 @@
|
||||
code : #96#56#0;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_SUB;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#241#160#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_SUB;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#235#160#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_SUB;
|
||||
ops : 3;
|
||||
optypes : (ot_reg32,ot_reg32,ot_shifterop,ot_none,ot_none,ot_none);
|
||||
code : #128#235#160#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_SUB;
|
||||
ops : 3;
|
||||
@ -2758,6 +2975,13 @@
|
||||
code : #96#65#0;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_ASR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #130#234#79#0#32;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ASR;
|
||||
ops : 3;
|
||||
@ -2765,6 +2989,13 @@
|
||||
code : #130#234#79#0#32;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ASR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#250#64#240#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ASR;
|
||||
ops : 3;
|
||||
@ -2800,6 +3031,13 @@
|
||||
code : #96#64#192;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_LSR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #130#234#79#0#16;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_LSR;
|
||||
ops : 3;
|
||||
@ -2807,6 +3045,13 @@
|
||||
code : #130#234#79#0#16;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_LSR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#250#32#240#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_LSR;
|
||||
ops : 3;
|
||||
@ -2842,6 +3087,13 @@
|
||||
code : #96#64#128;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_LSL;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #130#234#79#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_LSL;
|
||||
ops : 3;
|
||||
@ -2849,6 +3101,13 @@
|
||||
code : #130#234#79#0#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_LSL;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#250#96#240#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_LSL;
|
||||
ops : 3;
|
||||
@ -2877,6 +3136,13 @@
|
||||
code : #96#65#192;
|
||||
flags : if_thumb or if_armv4t
|
||||
),
|
||||
(
|
||||
opcode : A_ROR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #130#234#79#0#48;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ROR;
|
||||
ops : 3;
|
||||
@ -2884,6 +3150,13 @@
|
||||
code : #130#234#79#0#48;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ROR;
|
||||
ops : 2;
|
||||
optypes : (ot_reg32,ot_reg32,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #128#250#96#240#0;
|
||||
flags : if_thumb32 or if_wide or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_ROR;
|
||||
ops : 3;
|
||||
@ -4263,6 +4536,20 @@
|
||||
code : #254;
|
||||
flags : if_arm32 or if_armv4
|
||||
),
|
||||
(
|
||||
opcode : A_TBB;
|
||||
ops : 1;
|
||||
optypes : (ot_memoryam2,ot_none,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #142#232#208#240#0;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_TBH;
|
||||
ops : 1;
|
||||
optypes : (ot_memoryam2,ot_none,ot_none,ot_none,ot_none,ot_none);
|
||||
code : #142#232#208#240#16;
|
||||
flags : if_thumb32 or if_armv6t2
|
||||
),
|
||||
(
|
||||
opcode : A_MOVW;
|
||||
ops : 2;
|
||||
|
||||
@ -1388,6 +1388,7 @@ Implementation
|
||||
objsymend : TObjSymbol;
|
||||
zerobuf : array[0..63] of byte;
|
||||
relative_reloc: boolean;
|
||||
tmp : word;
|
||||
begin
|
||||
fillchar(zerobuf,sizeof(zerobuf),0);
|
||||
fillchar(objsym,sizeof(objsym),0);
|
||||
@ -1511,6 +1512,11 @@ Implementation
|
||||
aitconst_darwin_dwarf_delta32,
|
||||
aitconst_darwin_dwarf_delta64:
|
||||
ObjData.writebytes(Tai_const(hp).value,tai_const(hp).size);
|
||||
aitconst_half16bit:
|
||||
begin
|
||||
tmp:=Tai_const(hp).value div 2;
|
||||
ObjData.writebytes(tmp,2);
|
||||
end
|
||||
else
|
||||
internalerror(200603254);
|
||||
end;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user