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* fixed tinterlockedmt*.pp for architectures with weak memory consistency
models git-svn-id: trunk@41164 -
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@ -208,6 +208,8 @@ begin
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end;
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end;
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{ ensure the writes to Counter and Counter2 are ordered vs the writes to FinishedCount }
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WriteBarrier;
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InterLockedIncrement64(FinishedCount);
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end;
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@ -293,6 +295,10 @@ begin
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if t = 0 then
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t:=1/MSecsPerDay;
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{ ensure the read from FinishedCount above is ordered relative to the reads from
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Counter and Counter2 (counterpart to WriteBarrier in the thread function) }
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ReadBarrier();
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CheckResult(Counter, 0, 20, 'Counter error:');
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CheckResult(Counter2, (LastCompareVal - 2)*CmpCount, 21, 'Counter2 error:');
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@ -204,6 +204,9 @@ begin
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end;
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end;
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{ ensure the writes to Counter and Counter2 are ordered vs the writes to FinishedCount }
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WriteBarrier;
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InterLockedIncrement(FinishedCount);
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end;
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@ -288,6 +291,10 @@ begin
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if t = 0 then
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t:=1/MSecsPerDay;
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{ ensure the read from FinishedCount above is ordered relative to the reads from
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Counter and Counter2 (counterpart to WriteBarrier in the thread function) }
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ReadBarrier();
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CheckResult(Counter, 0, 20, 'Counter error:');
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CheckResult(Counter2, (LastCompareVal - 2)*CmpCount, 21, 'Counter2 error:');
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