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* set index register correctly * index register might not be changed

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git-svn-id: trunk@22229 -
This commit is contained in:
florian 2012-08-24 09:16:38 +00:00
parent 245d8286d5
commit 58a85e79ce
1 changed files with 5 additions and 2 deletions
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7
compiler/arm/aoptcpu.pas
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@ -380,7 +380,10 @@ Implementation
(taicpu(hp1).oper[1]^.reg=p.oper[1]^.ref^.base) and (taicpu(hp1).oper[1]^.reg=p.oper[1]^.ref^.base) and
{ don't apply the optimization if the base register is loaded } { don't apply the optimization if the base register is loaded }
(p.oper[0]^.reg<>p.oper[1]^.ref^.base) and (p.oper[0]^.reg<>p.oper[1]^.ref^.base) and
not(RegModifiedBetween(taicpu(hp1).oper[0]^.reg,p,hp1)) then not(RegModifiedBetween(taicpu(hp1).oper[0]^.reg,p,hp1)) and
{ don't apply the optimization if the (new) index register is loaded }
(p.oper[0]^.reg<>taicpu(hp1).oper[2]^.reg) and
not(RegModifiedBetween(taicpu(hp1).oper[2]^.reg,p,hp1)) then
begin begin
DebugMsg('Peephole Str/LdrAdd/Sub2Str/Ldr Postindex done', p); DebugMsg('Peephole Str/LdrAdd/Sub2Str/Ldr Postindex done', p);
p.oper[1]^.ref^.addressmode:=AM_POSTINDEXED; p.oper[1]^.ref^.addressmode:=AM_POSTINDEXED;
@ -393,7 +396,7 @@ Implementation
end end
else else
begin begin
p.oper[1]^.ref^.index:=taicpu(hp1).oper[1]^.reg; p.oper[1]^.ref^.index:=taicpu(hp1).oper[2]^.reg;
if taicpu(hp1).opcode=A_ADD then if taicpu(hp1).opcode=A_ADD then
p.oper[1]^.ref^.signindex:=1 p.oper[1]^.ref^.signindex:=1
else else