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Don't emit useless AND/BICs in ARM CG

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In certain cases the CG would emit something like
bic r1, r0, #0
As BIC is clearing the specified bits this is equivalent to
mov r1, r0
This patch changes the CG to emit the mov instead which the register
allocator will hopefully remove most of the time.

git-svn-id: trunk@22024 -
This commit is contained in:
masta 2012-08-07 06:46:45 +00:00
parent 9e039936bf
commit 6529307d9e
1 changed files with 2 additions and 0 deletions
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2
compiler/arm/cgcpu.pas
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@ -765,6 +765,8 @@ unit cgcpu;
end
{ BIC clears the specified bits, while AND keeps them, using BIC allows to use a
broader range of shifterconstants.}
else if (op = OP_AND) and (not(dword(a))=0) then
list.concat(taicpu.op_reg_reg(A_MOV,dst,src))
else if (op = OP_AND) and is_shifter_const(not(dword(a)),shift) then
list.concat(taicpu.op_reg_reg_const(A_BIC,dst,src,not(dword(a))))
else if (op = OP_AND) and split_into_shifter_const(not(dword(a)), imm1, imm2) then