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* patch by Christo Crause: support for megaAVR 0 and tinyAVR 0/1, #36616, part 1/3
git-svn-id: trunk@44036 -
This commit is contained in:
florian
parent
5aaf68b088
commit
670c61e760
@ -433,13 +433,21 @@ Implementation
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(getsupreg(taicpu(p).oper[0]^.ref^.base)=RS_NO) and
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(getsupreg(taicpu(p).oper[0]^.ref^.index)=RS_NO) and
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(taicpu(p).oper[0]^.ref^.addressmode=AM_UNCHANGED) and
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(taicpu(p).oper[0]^.ref^.offset>=32) and
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(taicpu(p).oper[0]^.ref^.offset<=95) then
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// avrxmega3 doesn't map registers into data space so no offset to subtract
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(((current_settings.cputype = cpu_avrxmega3) and
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(taicpu(p).oper[0]^.ref^.offset>=0) and
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(taicpu(p).oper[0]^.ref^.offset<=63)) or
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((current_settings.cputype <> cpu_avrxmega3) and
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(taicpu(p).oper[0]^.ref^.offset>=32) and
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(taicpu(p).oper[0]^.ref^.offset<=95))) then
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begin
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DebugMsg('Peephole Sts2Out performed', p);
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taicpu(p).opcode:=A_OUT;
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taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset-32);
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if current_settings.cputype = cpu_avrxmega3 then
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taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset)
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else
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taicpu(p).loadconst(0,taicpu(p).oper[0]^.ref^.offset-32);
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end;
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A_LDS:
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if (taicpu(p).oper[1]^.ref^.symbol=nil) and
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@ -447,13 +455,21 @@ Implementation
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(getsupreg(taicpu(p).oper[1]^.ref^.base)=RS_NO) and
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(getsupreg(taicpu(p).oper[1]^.ref^.index)=RS_NO) and
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(taicpu(p).oper[1]^.ref^.addressmode=AM_UNCHANGED) and
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(taicpu(p).oper[1]^.ref^.offset>=32) and
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(taicpu(p).oper[1]^.ref^.offset<=95) then
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// avrxmega3 doesn't map registers into data space so no offset to subtract
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(((current_settings.cputype = cpu_avrxmega3) and
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(taicpu(p).oper[1]^.ref^.offset>=0) and
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(taicpu(p).oper[1]^.ref^.offset<=63)) or
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((current_settings.cputype <> cpu_avrxmega3) and
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(taicpu(p).oper[1]^.ref^.offset>=32) and
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(taicpu(p).oper[1]^.ref^.offset<=95))) then
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begin
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DebugMsg('Peephole Lds2In performed', p);
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taicpu(p).opcode:=A_IN;
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taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset-32);
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if current_settings.cputype = cpu_avrxmega3 then
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taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset)
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else
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taicpu(p).loadconst(1,taicpu(p).oper[1]^.ref^.offset-32);
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end;
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A_IN:
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if GetNextInstruction(p,hp1) then
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@ -1375,8 +1375,11 @@ unit cgcpu;
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// Write to 16 bit ioreg, first high byte then low byte
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// sequence required for 16 bit timer registers
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// See e.g. atmega328p manual para 15.3 Accessing 16 bit registers
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if (fromsize in [OS_16, OS_S16]) and QuickRef and (href.offset > 31)
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and (href.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then
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// Avrxmega3: write low byte first then high byte
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// See e.g. megaAVR-0 family data sheet 7.5.6 Accessing 16-bit registers
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if (current_settings.cputype <> cpu_avrxmega3) and
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(fromsize in [OS_16, OS_S16]) and QuickRef and (href.offset > 31) and
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(href.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then
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begin
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tmpreg:=GetNextReg(reg);
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href.addressmode:=AM_UNCHANGED;
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@ -2592,23 +2595,24 @@ unit cgcpu;
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dstref:=dest;
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end;
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// CC
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// If dest is an ioreg (31 < offset < srambase) and size = 16 bit then
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// load high byte first, then low byte
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if (len = 2) and DestQuickRef
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and (dest.offset > 31)
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and (dest.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then
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begin
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// If src is also a 16 bit ioreg then read low byte then high byte
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if SrcQuickRef and (srcref.offset > 31)
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and (srcref.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then
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begin
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// First read source into temp registers
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tmpreg:=getintregister(list, OS_16);
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list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref));
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inc(srcref.offset);
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tmpreg2:=GetNextReg(tmpreg);
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list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg2,srcref));
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// CC
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// If dest is an ioreg (31 < offset < srambase) and size = 16 bit then
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// write high byte first, then low byte
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// but not for avrxmega3
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if (len = 2) and DestQuickRef and (current_settings.cputype <> cpu_avrxmega3) and
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(dest.offset > 31) and
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(dest.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then
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begin
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// If src is also a 16 bit ioreg then read low byte then high byte
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if SrcQuickRef and (srcref.offset > 31)
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and (srcref.offset < cpuinfo.embedded_controllers[current_settings.controllertype].srambase) then
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begin
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// First read source into temp registers
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tmpreg:=getintregister(list, OS_16);
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list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg,srcref));
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inc(srcref.offset);
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tmpreg2:=GetNextReg(tmpreg);
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list.concat(taicpu.op_reg_ref(GetLoad(srcref),tmpreg2,srcref));
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// then move temp registers to dest in reverse order
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inc(dstref.offset);
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@ -47,7 +47,8 @@ Type
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cpu_avr4,
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cpu_avr5,
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cpu_avr51,
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cpu_avr6
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cpu_avr6,
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cpu_avrxmega3
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);
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tfputype =
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@ -204,7 +205,42 @@ Type
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ct_atmega325,
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ct_atmega169pa,
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ct_attiny261a,
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ct_attiny25
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ct_attiny25,
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ct_atmega808,
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ct_atmega809,
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ct_atmega1608,
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ct_atmega1609,
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ct_atmega3208,
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ct_atmega3209,
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ct_atmega4808,
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ct_atmega4809,
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ct_attiny202,
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ct_attiny204,
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ct_attiny212,
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ct_attiny214,
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ct_attiny402,
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ct_attiny404,
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ct_attiny406,
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ct_attiny412,
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ct_attiny414,
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ct_attiny416,
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ct_attiny416auto,
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ct_attiny417,
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ct_attiny804,
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ct_attiny806,
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ct_attiny807,
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ct_attiny814,
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ct_attiny816,
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ct_attiny817,
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ct_attiny1604,
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ct_attiny1606,
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ct_attiny1607,
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ct_attiny1614,
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ct_attiny1616,
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ct_attiny1617,
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ct_attiny3214,
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ct_attiny3216,
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ct_attiny3217
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);
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tcontrollerdatatype = record
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@ -235,7 +271,7 @@ Const
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pocall_softfloat
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];
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cputypestr : array[tcputype] of string[8] = ('',
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cputypestr : array[tcputype] of string[9] = ('',
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'AVRTINY',
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'AVR1',
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'AVR2',
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@ -246,7 +282,8 @@ Const
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'AVR4',
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'AVR5',
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'AVR51',
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'AVR6'
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'AVR6',
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'AVRXMEGA3'
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);
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fputypestr : array[tfputype] of string[6] = (
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@ -428,6 +465,43 @@ Const
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,(controllertypestr:'ATMEGA169PA'; controllerunitstr:'ATMEGA169PA'; cputype: cpu_avr5; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:256; sramsize:1024; eeprombase:0; eepromsize:512)
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,(controllertypestr:'ATTINY261A'; controllerunitstr:'ATTINY261A'; cputype: cpu_avr25; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:96; sramsize:128; eeprombase:0; eepromsize:128)
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,(controllertypestr:'ATTINY25'; controllerunitstr:'ATTINY25'; cputype: cpu_avr25; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:96; sramsize:128; eeprombase:0; eepromsize:128)
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// megaAVR0 series
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,(controllertypestr:'ATMEGA808'; controllerunitstr:'ATMEGA808'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATMEGA809'; controllerunitstr:'ATMEGA809'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATMEGA1608'; controllerunitstr:'ATMEGA1608'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATMEGA1609'; controllerunitstr:'ATMEGA1609'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATMEGA3208'; controllerunitstr:'ATMEGA3208'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:12288; sramsize:4096; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATMEGA3209'; controllerunitstr:'ATMEGA3209'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:12288; sramsize:4096; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATMEGA4808'; controllerunitstr:'ATMEGA4808'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:49152; srambase:10240; sramsize:6144; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATMEGA4809'; controllerunitstr:'ATMEGA4809'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:49152; srambase:10240; sramsize:6144; eeprombase:5120; eepromsize:256)
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// tinyAVR 0/1 series
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,(controllertypestr:'ATTINY202'; controllerunitstr:'ATTINY202'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:16256; sramsize:128; eeprombase:5120; eepromsize:64)
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,(controllertypestr:'ATTINY204'; controllerunitstr:'ATTINY204'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:16256; sramsize:128; eeprombase:5120; eepromsize:64)
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,(controllertypestr:'ATTINY212'; controllerunitstr:'ATTINY212'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:16256; sramsize:128; eeprombase:5120; eepromsize:64)
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,(controllertypestr:'ATTINY214'; controllerunitstr:'ATTINY214'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:2048; srambase:16256; sramsize:128; eeprombase:5120; eepromsize:64)
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,(controllertypestr:'ATTINY402'; controllerunitstr:'ATTINY402'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY404'; controllerunitstr:'ATTINY404'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY406'; controllerunitstr:'ATTINY406'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY412'; controllerunitstr:'ATTINY412'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY414'; controllerunitstr:'ATTINY414'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY416'; controllerunitstr:'ATTINY416'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY416AUTO'; controllerunitstr:'ATTINY416AUTO'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY417'; controllerunitstr:'ATTINY417'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:4096; srambase:16128; sramsize:256; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY804'; controllerunitstr:'ATTINY804'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY806'; controllerunitstr:'ATTINY806'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY807'; controllerunitstr:'ATTINY807'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY814'; controllerunitstr:'ATTINY814'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY816'; controllerunitstr:'ATTINY816'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY817'; controllerunitstr:'ATTINY817'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:8192; srambase:15872; sramsize:512; eeprombase:5120; eepromsize:128)
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,(controllertypestr:'ATTINY1604'; controllerunitstr:'ATTINY1604'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATTINY1606'; controllerunitstr:'ATTINY1606'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATTINY1607'; controllerunitstr:'ATTINY1607'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:15360; sramsize:1024; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATTINY1614'; controllerunitstr:'ATTINY1614'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATTINY1616'; controllerunitstr:'ATTINY1616'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATTINY1617'; controllerunitstr:'ATTINY1617'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:16384; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATTINY3214'; controllerunitstr:'ATTINY3214'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATTINY3216'; controllerunitstr:'ATTINY3216'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256)
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,(controllertypestr:'ATTINY3217'; controllerunitstr:'ATTINY3217'; cputype: cpu_avrxmega3; fputype:fpu_soft; flashbase:0; flashsize:32768; srambase:14336; sramsize:2048; eeprombase:5120; eepromsize:256)
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);
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{ Supported optimizations, only used for information }
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@ -461,18 +535,19 @@ Const
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags =
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( { cpu_none } [],
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{ cpu_avrtiny } [CPUAVR_16_REGS,CPUAVR_2_BYTE_PC],
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{ cpu_avr1 } [CPUAVR_2_BYTE_PC],
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{ cpu_avr2 } [CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC],
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{ cpu_avr25 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC],
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{ cpu_avr3 } [CPUAVR_HAS_JMP_CALL,CPUAVR_2_BYTE_PC],
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{ cpu_avr31 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_2_BYTE_PC],
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{ cpu_avr35 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC],
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{ cpu_avr4 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC],
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{ cpu_avr5 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC],
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{ cpu_avr51 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_2_BYTE_PC],
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{ cpu_avr6 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_3_BYTE_PC]
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( { cpu_none } [],
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{ cpu_avrtiny } [CPUAVR_16_REGS,CPUAVR_2_BYTE_PC],
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{ cpu_avr1 } [CPUAVR_2_BYTE_PC],
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{ cpu_avr2 } [CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC],
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{ cpu_avr25 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC],
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{ cpu_avr3 } [CPUAVR_HAS_JMP_CALL,CPUAVR_2_BYTE_PC],
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{ cpu_avr31 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_2_BYTE_PC],
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{ cpu_avr35 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_2_BYTE_PC],
|
||||
{ cpu_avr4 } [CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC],
|
||||
{ cpu_avr5 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC],
|
||||
{ cpu_avr51 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_2_BYTE_PC],
|
||||
{ cpu_avr6 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_HAS_RAMPZ,CPUAVR_HAS_ELPM,CPUAVR_HAS_ELPMX,CPUAVR_3_BYTE_PC],
|
||||
{ cpu_avrxmega3 } [CPUAVR_HAS_JMP_CALL,CPUAVR_HAS_MOVW,CPUAVR_HAS_LPMX,CPUAVR_HAS_MUL,CPUAVR_2_BYTE_PC]
|
||||
);
|
||||
|
||||
Implementation
|
||||
|
||||
@ -824,6 +824,8 @@ begin
|
||||
Add('OUTPUT_ARCH(avr:51)');
|
||||
cpu_avr6:
|
||||
Add('OUTPUT_ARCH(avr:6)');
|
||||
cpu_avrxmega3:
|
||||
Add('OUTPUT_ARCH(avr:103)');
|
||||
else
|
||||
Internalerror(2015072701);
|
||||
end;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user