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* RiscV64: optimize 32 bit shift instructions as well

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florian 2025-01-04 14:58:31 +01:00
parent 863fe13bd1
commit 72daf3f556
1 changed files with 10 additions and 0 deletions
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10
compiler/riscv/aoptcpurv.pas
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@ -680,12 +680,22 @@ implementation
A_AND,
A_OR,
A_XOR,
{$ifdef riscv64}
A_SLLW,
A_SRLW,
A_SRAW,
{$endif riscv64}
A_SLL,
A_SRL,
A_SRA,
A_NEG,
A_NOT:
result:=OptPass1OP(p);
{$ifdef riscv64}
A_SRAIW,
A_SRLIW,
A_SLLIW,
{$endif riscv64}
A_SRAI,
A_SRLI,
A_SLLI: