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* RiscV32 correctly set operands of div/mod operations, resolves

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git-svn-id: trunk@46859 -
This commit is contained in:
florian 2020-09-12 21:32:11 +00:00
parent d7fe9914a7
commit 7f8f733963
1 changed files with 2 additions and 2 deletions

4
compiler/riscv32/nrv32mat.pas
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@ -100,7 +100,7 @@ implementation
else
op:=A_DIVU;
current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,denum,num,denum));
current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,num,num,denum));
end;
procedure trv32moddivnode.emit_mod_reg_reg(signed: boolean; denum, num: tregister);
@ -112,7 +112,7 @@ implementation
else
op:=A_REMU;
current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,denum,num,denum));
current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(op,num,num,denum));
end;