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Fix a broken OpCp2Op optimization. It needed the added NR_DEFAULTFLAGS allocation to not break subsequent optimizations.

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Updated the code for a_load_const_cgpara in case it needed stack parameters. This was completely broken before. Now it should allow things to compile at least.

git-svn-id: trunk@32086 -
This commit is contained in:
Jeppe Johansen 2015-10-17 23:29:15 +00:00
parent 9193954d1c
commit 7fc3ed2644
2 changed files with 31 additions and 10 deletions
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26
compiler/avr/aoptcpu.pas
View File

@ -171,14 +171,19 @@ Implementation
A_INC,A_LSL,A_LSR,
A_OR,A_ORI,A_ROL,A_ROR,A_SBC,A_SBCI,A_SUB,A_SUBI]) and
GetNextInstruction(p, hp1) and
MatchInstruction(hp1, A_CP) and
(((taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
(taicpu(hp1).oper[1]^.reg = NR_R1)) or
((taicpu(p).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
(taicpu(hp1).oper[0]^.reg = NR_R1) and
(taicpu(p).opcode in [A_ADC,A_ADD,A_AND,A_ANDI,A_ASR,A_COM,A_EOR,
A_LSL,A_LSR,
A_OR,A_ORI,A_ROL,A_ROR]))) and
((MatchInstruction(hp1, A_CP) and
(((taicpu(p).oper[0]^.reg = taicpu(hp1).oper[0]^.reg) and
(taicpu(hp1).oper[1]^.reg = NR_R1)) or
((taicpu(p).oper[0]^.reg = taicpu(hp1).oper[1]^.reg) and
(taicpu(hp1).oper[0]^.reg = NR_R1) and
(taicpu(p).opcode in [A_ADC,A_ADD,A_AND,A_ANDI,A_ASR,A_COM,A_EOR,
A_LSL,A_LSR,
A_OR,A_ORI,A_ROL,A_ROR])))) or
(MatchInstruction(hp1, A_CPI) and
(taicpu(p).opcode in [A_ANDI,A_ORI]) and
(taicpu(p).oper[1]^.typ=top_const) and
(taicpu(hp1).oper[1]^.typ=top_const) and
(taicpu(p).oper[1]^.val=taicpu(hp1).oper[1]^.val))) and
GetNextInstruction(hp1, hp2) and
{ be careful here, following instructions could use other flags
however after a jump fpc never depends on the value of flags }
@ -203,6 +208,10 @@ Implementation
end;
}
asml.InsertBefore(tai_regalloc.alloc(NR_DEFAULTFLAGS,p), p);
asml.InsertAfter(tai_regalloc.dealloc(NR_DEFAULTFLAGS,hp2), hp2);
IncludeRegInUsedRegs(NR_DEFAULTFLAGS,UsedRegs);
DebugMsg('Peephole OpCp2Op performed', p);
asml.remove(hp1);
@ -584,6 +593,7 @@ Implementation
(not RegModifiedBetween(taicpu(p).oper[1]^.reg, p, hp1)) and
(hp1.typ = ait_instruction) and
(taicpu(hp1).opcode in [A_PUSH,A_MOV,A_CP,A_CPC,A_ADD,A_SUB,A_ADC,A_SBC,A_EOR,A_AND,A_OR,
A_STD,A_ST,
A_OUT,A_IN]) and
RegInInstruction(taicpu(p).oper[0]^.reg, hp1) and
(not RegModifiedByInstruction(taicpu(p).oper[0]^.reg, hp1)) and

15
compiler/avr/cgcpu.pas
View File

@ -308,13 +308,15 @@ unit cgcpu;
var
i : longint;
hp : PCGParaLocation;
ref: treference;
begin
if not(tcgsize2size[paraloc.Size] in [1..4]) then
internalerror(2014011101);
hp:=paraloc.location;
for i:=1 to tcgsize2size[paraloc.Size] do
i:=1;
while i<tcgsize2size[paraloc.Size] do
begin
if not(assigned(hp)) then
internalerror(2014011105);
@ -326,9 +328,18 @@ unit cgcpu;
internalerror(2015041101);
a_load_const_reg(list,hp^.size,(a shr (8*(i-1))) and $ff,hp^.register);
hp:=hp^.Next;
inc(i);
end;
LOC_REFERENCE,LOC_CREFERENCE:
list.concat(taicpu.op_const(A_PUSH,(a shr (8*(i-1))) and $ff));
begin
reference_reset(ref,paraloc.alignment);
ref.base:=hp^.reference.index;
ref.offset:=hp^.reference.offset;
a_load_const_ref(list,hp^.size,a shr (8*(i-1)),ref);
inc(i,tcgsize2size[hp^.size]);
hp:=hp^.Next;
end;
else
internalerror(2002071004);
end;