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* don't write the destination register in a_load_ref_reg_unaligned() before

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the reference has been used for the last time, as the destination
    register could be the base or index register of the reference

git-svn-id: trunk@33393 -
This commit is contained in:
Jonas Maebe 2016-03-30 20:04:31 +00:00
parent 2221e4e4bd
commit 8c0d9b581c
3 changed files with 45 additions and 1 deletions
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1
.gitattributes vendored
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@ -10875,6 +10875,7 @@ tests/tbs/tb0614.pp svneol=native#text/pascal
tests/tbs/tb0615.pp svneol=native#text/pascal
tests/tbs/tb0616.pp svneol=native#text/pascal
tests/tbs/tb0617.pp svneol=native#text/pascal
tests/tbs/tb0618.pp svneol=native#text/plain
tests/tbs/tb205.pp svneol=native#text/plain
tests/tbs/tb610.pp svneol=native#text/pascal
tests/tbs/tb613.pp svneol=native#text/plain

3
compiler/aarch64/cgcpu.pas
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@ -812,7 +812,7 @@ implementation
if fromsize in [OS_64,OS_S64] then
begin
{ split into two 32 bit loads }
hreg1:=makeregsize(register,OS_32);
hreg1:=getintregister(list,OS_32);
hreg2:=getintregister(list,OS_32);
if target_info.endian=endian_big then
begin
@ -831,6 +831,7 @@ implementation
inc(href.offset,4);
a_load_ref_reg(list,OS_32,OS_32,href,hreg2);
end;
a_load_reg_reg(list,OS_32,OS_64,hreg1,register);
list.concat(taicpu.op_reg_reg_const_const(A_BFI,register,makeregsize(hreg2,OS_64),32,32));
end
else

42
tests/tbs/tb0618.pp Normal file
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@ -0,0 +1,42 @@
type
PStreamRec= ^TStreamRec;
TStreamRec = Packed Record
ObjType : byte;
Next : PStreamRec;
end;
const
BaseRec : PStreamRec= nil;
RType1 : TStreamRec = (
ObjType : 79
);
RType2 : TStreamRec = (
objtype : 80
);
procedure RegisterType(var R : TStreamRec);
var
P : PStreamRec;
begin
P := BaseRec;
while (P <> nil) and (P^.Objtype <> R.ObjType) do
P:=P^.Next;
if not assigned(P) then
begin
R.Next:=BaseRec;
BaseRec:=@R;
end;
{ nothing to do here
else
P:=@R; }
end;
begin
RegisterType(Rtype1);
RegisterType(RType2);
end.