mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-08-14 04:42:31 +02:00
* tcg8086.a_op_const_ref and .a_op_const_reg: when splitting a 32-bit OP_AND,
OP_OR or OP_XOR operation into two 16-bit parts, call a_op_const_reg/ref recursively for the 16-bit parts, so certain optimizations can be done if the low or high 16-bit of the const are $ffff. git-svn-id: trunk@25703 -
This commit is contained in:
parent
1f11c39a5d
commit
8f44e729cc
@ -290,10 +290,15 @@ unit cgcpu;
|
|||||||
{ Optimized, replaced with a simple load }
|
{ Optimized, replaced with a simple load }
|
||||||
a_load_const_reg(list,size,a,reg);
|
a_load_const_reg(list,size,a,reg);
|
||||||
end;
|
end;
|
||||||
OP_ADD, OP_AND, OP_OR, OP_SUB, OP_XOR:
|
OP_ADD, OP_SUB:
|
||||||
begin
|
begin
|
||||||
if (longword(a) = high(longword)) and
|
get_32bit_ops(op, op1, op2);
|
||||||
(op in [OP_AND,OP_OR,OP_XOR]) then
|
list.concat(taicpu.op_const_reg(op1,S_W,aint(a and $FFFF),reg));
|
||||||
|
list.concat(taicpu.op_const_reg(op2,S_W,aint(a shr 16),GetNextReg(reg)));
|
||||||
|
end;
|
||||||
|
OP_AND, OP_OR, OP_XOR:
|
||||||
|
begin
|
||||||
|
if longword(a) = high(longword) then
|
||||||
begin
|
begin
|
||||||
case op of
|
case op of
|
||||||
OP_AND:
|
OP_AND:
|
||||||
@ -305,13 +310,14 @@ unit cgcpu;
|
|||||||
list.concat(taicpu.op_reg(A_NOT,S_W,reg));
|
list.concat(taicpu.op_reg(A_NOT,S_W,reg));
|
||||||
list.concat(taicpu.op_reg(A_NOT,S_W,GetNextReg(reg)));
|
list.concat(taicpu.op_reg(A_NOT,S_W,GetNextReg(reg)));
|
||||||
end;
|
end;
|
||||||
|
else
|
||||||
|
InternalError(2013100701);
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
else
|
else
|
||||||
begin
|
begin
|
||||||
get_32bit_ops(op, op1, op2);
|
a_op_const_reg(list,op,OS_16,aint(a and $FFFF),reg);
|
||||||
list.concat(taicpu.op_const_reg(op1,S_W,aint(a and $FFFF),reg));
|
a_op_const_reg(list,op,OS_16,aint(a shr 16),GetNextReg(reg));
|
||||||
list.concat(taicpu.op_const_reg(op2,S_W,aint(a shr 16),GetNextReg(reg)));
|
|
||||||
end;
|
end;
|
||||||
end;
|
end;
|
||||||
OP_SHR,OP_SHL,OP_SAR:
|
OP_SHR,OP_SHL,OP_SAR:
|
||||||
@ -493,10 +499,16 @@ unit cgcpu;
|
|||||||
{ Optimized, replaced with a simple load }
|
{ Optimized, replaced with a simple load }
|
||||||
a_load_const_ref(list,size,a,ref);
|
a_load_const_ref(list,size,a,ref);
|
||||||
end;
|
end;
|
||||||
OP_ADD, OP_AND, OP_OR, OP_SUB, OP_XOR:
|
OP_ADD, OP_SUB:
|
||||||
begin
|
begin
|
||||||
if (longword(a) = high(longword)) and
|
get_32bit_ops(op, op1, op2);
|
||||||
(op in [OP_AND,OP_OR,OP_XOR]) then
|
list.concat(taicpu.op_const_ref(op1,S_W,aint(a and $FFFF),tmpref));
|
||||||
|
inc(tmpref.offset, 2);
|
||||||
|
list.concat(taicpu.op_const_ref(op2,S_W,aint(a shr 16),tmpref));
|
||||||
|
end;
|
||||||
|
OP_AND, OP_OR, OP_XOR:
|
||||||
|
begin
|
||||||
|
if longword(a) = high(longword) then
|
||||||
begin
|
begin
|
||||||
case op of
|
case op of
|
||||||
OP_AND:
|
OP_AND:
|
||||||
@ -509,14 +521,15 @@ unit cgcpu;
|
|||||||
inc(tmpref.offset, 2);
|
inc(tmpref.offset, 2);
|
||||||
list.concat(taicpu.op_ref(A_NOT,S_W,tmpref));
|
list.concat(taicpu.op_ref(A_NOT,S_W,tmpref));
|
||||||
end;
|
end;
|
||||||
|
else
|
||||||
|
InternalError(2013100701);
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
else
|
else
|
||||||
begin
|
begin
|
||||||
get_32bit_ops(op, op1, op2);
|
a_op_const_ref(list,op,OS_16,aint(a and $FFFF),tmpref);
|
||||||
list.concat(taicpu.op_const_ref(op1,S_W,aint(a and $FFFF),tmpref));
|
|
||||||
inc(tmpref.offset, 2);
|
inc(tmpref.offset, 2);
|
||||||
list.concat(taicpu.op_const_ref(op2,S_W,aint(a shr 16),tmpref));
|
a_op_const_ref(list,op,OS_16,aint(a shr 16),tmpref);
|
||||||
end;
|
end;
|
||||||
end;
|
end;
|
||||||
else
|
else
|
||||||
|
Loading…
Reference in New Issue
Block a user