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Add CBNZ/CBZ instructions
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code Added a number of simple size optimizations for common Thumb-2 instructions git-svn-id: branches/laksen/arm-embedded@22590 -
This commit is contained in:
Jeppe Johansen
parent
b788ba660d
commit
9ec9b44784
@ -175,6 +175,7 @@ uses
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constructor op_reg_ref(op : tasmop;_op1 : tregister;const _op2 : treference);
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constructor op_reg_const(op:tasmop; _op1: tregister; _op2: aint);
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constructor op_regset(op:tasmop; regtype: tregistertype; subreg: tsubregister; _op1: tcpuregisterset);
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constructor op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
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constructor op_reg_reg_reg(op : tasmop;_op1,_op2,_op3 : tregister);
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@ -415,6 +416,13 @@ implementation
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loadconst(1,aint(_op2));
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end;
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constructor taicpu.op_regset(op: tasmop; regtype: tregistertype; subreg: tsubregister; _op1: tcpuregisterset);
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begin
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inherited create(op);
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ops:=1;
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loadregset(0,regtype,subreg,_op1);
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end;
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constructor taicpu.op_ref_regset(op:tasmop; _op1: treference; regtype: tregistertype; subreg: tsubregister; _op2: tcpuregisterset);
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begin
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@ -30,7 +30,7 @@ Unit aoptcpu;
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Interface
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uses cgbase, cpubase, aasmtai, aasmcpu,aopt, aoptcpub, aoptobj;
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uses cgbase, cpubase, aasmtai, aasmcpu,aopt, aoptcpub, aoptobj, cclasses;
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Type
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TCpuAsmOptimizer = class(TAsmOptimizer)
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@ -62,6 +62,7 @@ Type
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TCpuThumb2AsmOptimizer = class(TCpuAsmOptimizer)
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{ uses the same constructor as TAopObj }
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function PeepHoleOptPass1Cpu(var p: tai): boolean; override;
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procedure PeepHoleOptPass2;override;
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End;
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@ -80,6 +81,8 @@ Implementation
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(p.typ=ait_instruction) and
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(taicpu(p).condition=C_None) and
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((taicpu(p).opcode<A_IT) or (taicpu(p).opcode>A_ITTTT)) and
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(taicpu(p).opcode<>A_CBZ) and
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(taicpu(p).opcode<>A_CBNZ) and
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(taicpu(p).opcode<>A_PLD) and
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((taicpu(p).opcode<>A_BLX) or
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(taicpu(p).oper[0]^.typ=top_reg));
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@ -327,6 +330,9 @@ Implementation
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(taicpu(movp).oper[0]^.reg<>NR_R14) and
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{ the destination register of the mov might not be used beween p and movp }
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not(RegUsedBetween(taicpu(movp).oper[0]^.reg,p,movp)) and
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{ cb[n]z are thumb instructions which require specific registers, with no wide forms }
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(taicpu(p).opcode<>A_CBZ) and
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(taicpu(p).opcode<>A_CBNZ) and
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{There is a special requirement for MUL and MLA, oper[0] and oper[1] are not allowed to be the same}
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not (
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(taicpu(p).opcode in [A_MLA, A_MUL]) and
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@ -1152,6 +1158,85 @@ Implementation
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if GetNextInstructionUsingReg(p, hp1, taicpu(p).oper[0]^.reg) then
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RemoveSuperfluousMove(p, hp1, 'DataMov2Data');
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end;
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A_MVN:
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begin
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{
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change
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mvn reg2,reg1
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and reg3,reg4,reg2
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dealloc reg2
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to
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bic reg3,reg4,reg1
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}
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if (taicpu(p).oper[1]^.typ = top_reg) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1,A_AND,[],[]) and
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(((taicpu(hp1).ops=3) and
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(taicpu(hp1).oper[2]^.typ=top_reg) and
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(MatchOperand(taicpu(hp1).oper[2]^, taicpu(p).oper[0]^.reg) or
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg))) or
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((taicpu(hp1).ops=2) and
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(taicpu(hp1).oper[1]^.typ=top_reg) and
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MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg))) and
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assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) and
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{ reg1 might not be modified inbetween }
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
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begin
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DebugMsg('Peephole MvnAnd2Bic done', p);
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taicpu(hp1).opcode:=A_BIC;
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if taicpu(hp1).ops=3 then
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begin
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if MatchOperand(taicpu(hp1).oper[1]^, taicpu(p).oper[0]^.reg) then
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taicpu(hp1).loadReg(1,taicpu(hp1).oper[2]^.reg); // Swap operands
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taicpu(hp1).loadReg(2,taicpu(p).oper[1]^.reg);
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end
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else
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taicpu(hp1).loadReg(1,taicpu(p).oper[1]^.reg);
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asml.remove(p);
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p.free;
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p:=hp1;
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end;
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end;
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A_UXTB,
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A_SXTB:
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begin
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if MatchInstruction(p, taicpu(p).opcode, [C_None], [PF_None]) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1, A_STR, [C_None], [PF_B]) and
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assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) and
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{ the reference in strb might not use reg2 }
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not(RegInRef(taicpu(p).oper[0]^.reg,taicpu(hp1).oper[1]^.ref^)) and
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{ reg1 might not be modified inbetween }
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
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begin
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DebugMsg('Peephole xXTBStrb2Strb done', p);
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taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg);
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asml.remove(p);
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p.free;
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p:=hp1;
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end;
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end;
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A_UXTH,
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A_SXTH:
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begin
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if MatchInstruction(p, taicpu(p).opcode, [C_None], [PF_None]) and
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GetNextInstructionUsingReg(p,hp1,taicpu(p).oper[0]^.reg) and
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MatchInstruction(hp1, A_STR, [C_None], [PF_H]) and
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assigned(FindRegDealloc(taicpu(p).oper[0]^.reg,tai(hp1.Next))) and
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{ the reference in strb might not use reg2 }
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not(RegInRef(taicpu(p).oper[0]^.reg,taicpu(hp1).oper[1]^.ref^)) and
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{ reg1 might not be modified inbetween }
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not(RegModifiedBetween(taicpu(p).oper[1]^.reg,p,hp1)) then
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begin
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DebugMsg('Peephole xXTBStrh2Strh done', p);
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taicpu(hp1).loadReg(0,taicpu(p).oper[1]^.reg);
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asml.remove(p);
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p.free;
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p:=hp1;
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end;
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end;
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A_CMP:
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begin
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{
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@ -1566,9 +1651,340 @@ Implementation
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end;
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procedure TCpuThumb2AsmOptimizer.PeepHoleOptPass2;
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procedure DecrementPreceedingIT(list: TAsmList; p: tai);
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var
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hp : tai;
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l : longint;
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begin
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{ TODO: Add optimizer code }
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hp := tai(p.Previous);
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l := 1;
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while assigned(hp) and
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(l <= 4) do
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begin
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if hp.typ=ait_instruction then
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begin
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if (taicpu(hp).opcode>=A_IT) and
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(taicpu(hp).opcode <= A_ITTTT) then
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begin
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if (taicpu(hp).opcode = A_IT) and
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(l=1) then
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list.Remove(hp)
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else
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case taicpu(hp).opcode of
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A_ITE:
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if l=2 then taicpu(hp).opcode := A_IT;
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A_ITT:
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if l=2 then taicpu(hp).opcode := A_IT;
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A_ITEE:
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if l=3 then taicpu(hp).opcode := A_ITE;
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A_ITTE:
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if l=3 then taicpu(hp).opcode := A_ITT;
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A_ITET:
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if l=3 then taicpu(hp).opcode := A_ITE;
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A_ITTT:
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if l=3 then taicpu(hp).opcode := A_ITT;
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A_ITEEE:
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if l=4 then taicpu(hp).opcode := A_ITEE;
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A_ITTEE:
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if l=4 then taicpu(hp).opcode := A_ITTE;
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A_ITETE:
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if l=4 then taicpu(hp).opcode := A_ITET;
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A_ITTTE:
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if l=4 then taicpu(hp).opcode := A_ITTT;
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A_ITEET:
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if l=4 then taicpu(hp).opcode := A_ITEE;
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A_ITTET:
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if l=4 then taicpu(hp).opcode := A_ITTE;
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A_ITETT:
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if l=4 then taicpu(hp).opcode := A_ITET;
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A_ITTTT:
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if l=4 then taicpu(hp).opcode := A_ITTT;
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end;
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break;
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end;
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{else if (taicpu(hp).condition<>taicpu(p).condition) or
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(taicpu(hp).condition<>inverse_cond(taicpu(p).condition)) then
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break;}
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inc(l);
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end;
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hp := tai(hp.Previous);
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end;
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end;
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function TCpuThumb2AsmOptimizer.PeepHoleOptPass1Cpu(var p: tai): boolean;
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var
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hp : taicpu;
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hp1,hp2 : tai;
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begin
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if (p.typ=ait_instruction) and
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MatchInstruction(p, A_STM, [C_None], [PF_FD,PF_DB]) and
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(taicpu(p).oper[0]^.ref^.addressmode=AM_PREINDEXED) and
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(taicpu(p).oper[0]^.ref^.index=NR_STACK_POINTER_REG) and
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((taicpu(p).oper[1]^.regset^*[8..13,15])=[]) then
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begin
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hp := taicpu.op_regset(A_PUSH, R_INTREGISTER, R_SUBWHOLE, taicpu(p).oper[1]^.regset^);
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AsmL.InsertAfter(hp, p);
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asml.Remove(p);
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p:=hp;
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result:=true;
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end
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else if (p.typ=ait_instruction) and
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MatchInstruction(p, A_STR, [C_None], [PF_None]) and
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(taicpu(p).oper[1]^.ref^.addressmode=AM_PREINDEXED) and
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(taicpu(p).oper[1]^.ref^.index=NR_STACK_POINTER_REG) and
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(taicpu(p).oper[1]^.ref^.offset=-4) and
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(getsupreg(taicpu(p).oper[0]^.reg) in [0..7,14]) then
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begin
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hp := taicpu.op_regset(A_PUSH, R_INTREGISTER, R_SUBWHOLE, [getsupreg(taicpu(p).oper[0]^.reg)]);
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asml.InsertAfter(hp, p);
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asml.Remove(p);
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p.Free;
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p:=hp;
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result:=true;
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end
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else if (p.typ=ait_instruction) and
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MatchInstruction(p, A_LDM, [C_None], [PF_FD,PF_IA]) and
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(taicpu(p).oper[0]^.ref^.addressmode=AM_PREINDEXED) and
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(taicpu(p).oper[0]^.ref^.index=NR_STACK_POINTER_REG) and
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((taicpu(p).oper[1]^.regset^*[8..14])=[]) then
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begin
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hp := taicpu.op_regset(A_POP, R_INTREGISTER, R_SUBWHOLE, taicpu(p).oper[1]^.regset^);
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asml.InsertBefore(hp, p);
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asml.Remove(p);
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p.Free;
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p:=hp;
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result:=true;
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end
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else if (p.typ=ait_instruction) and
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MatchInstruction(p, A_LDR, [C_None], [PF_None]) and
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(taicpu(p).oper[1]^.ref^.addressmode=AM_POSTINDEXED) and
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(taicpu(p).oper[1]^.ref^.index=NR_STACK_POINTER_REG) and
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(taicpu(p).oper[1]^.ref^.offset=4) and
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(getsupreg(taicpu(p).oper[0]^.reg) in [0..7,15]) then
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begin
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hp := taicpu.op_regset(A_POP, R_INTREGISTER, R_SUBWHOLE, [getsupreg(taicpu(p).oper[0]^.reg)]);
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asml.InsertBefore(hp, p);
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asml.Remove(p);
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p.Free;
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p:=hp;
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result:=true;
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end
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else if (p.typ=ait_instruction) and
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MatchInstruction(p, A_MOV, [C_None], [PF_None]) and
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(taicpu(p).oper[1]^.typ=top_const) and
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(taicpu(p).oper[1]^.val >= 0) and
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(taicpu(p).oper[1]^.val < 256) and
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(not Assigned(FindRegDeAlloc(NR_DEFAULTFLAGS, p))) then
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begin
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taicpu(p).oppostfix:=PF_S;
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result:=true;
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end
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else if (p.typ=ait_instruction) and
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MatchInstruction(p, A_MVN, [], [PF_None]) and
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(taicpu(p).oper[1]^.typ=top_reg) and
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(not Assigned(FindRegDeAlloc(NR_DEFAULTFLAGS, p))) then
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begin
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taicpu(p).oppostfix:=PF_S;
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result:=true;
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end
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else if (p.typ=ait_instruction) and
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MatchInstruction(p, [A_ADD,A_SUB], [C_None], [PF_None]) and
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(taicpu(p).ops = 3) and
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MatchOperand(taicpu(p).oper[0]^, taicpu(p).oper[1]^) and
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(not MatchOperand(taicpu(p).oper[0]^, NR_STACK_POINTER_REG)) and
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(taicpu(p).oper[2]^.typ=top_const) and
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(taicpu(p).oper[2]^.val >= 0) and
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(taicpu(p).oper[2]^.val < 256) and
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(not Assigned(FindRegDeAlloc(NR_DEFAULTFLAGS, p))) then
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begin
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taicpu(p).loadconst(1,taicpu(p).oper[2]^.val);
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taicpu(p).oppostfix:=PF_S;
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taicpu(p).ops := 2;
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result:=true;
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end
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{else if (p.typ=ait_instruction) and
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MatchInstruction(p, [A_AND,A_ORR,A_EOR,A_LSL,A_LSR,A_ASR,A_ROR], [], [PF_None,PF_S]) and
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(taicpu(p).ops = 3) and
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MatchOperand(taicpu(p).oper[0]^, taicpu(p).oper[1]^) and
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(taicpu(p).oper[2]^.typ=top_reg) and
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(not Assigned(FindRegDeAlloc(NR_DEFAULTFLAGS, p))) then
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begin
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taicpu(p).ops := 2;
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taicpu(p).loadreg(1,taicpu(p).oper[2]^.reg);
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taicpu(p).oppostfix:=PF_S;
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result:=true;
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end
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else if (p.typ=ait_instruction) and
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MatchInstruction(p, [A_AND,A_ORR,A_EOR], [], [PF_None,PF_S]) and
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(taicpu(p).ops = 3) and
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MatchOperand(taicpu(p).oper[0]^, taicpu(p).oper[2]^) and
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(not Assigned(FindRegDeAlloc(NR_DEFAULTFLAGS, p))) then
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begin
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taicpu(p).oppostfix:=PF_S;
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taicpu(p).ops := 2;
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result:=true;
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end}
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else if (p.typ=ait_instruction) and
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MatchInstruction(p, [A_AND], [], [PF_None]) and
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(taicpu(p).ops = 2) and
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(taicpu(p).oper[1]^.typ=top_const) and
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((taicpu(p).oper[1]^.val=255) or
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(taicpu(p).oper[1]^.val=65535)) then
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begin
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if taicpu(p).oper[1]^.val=255 then
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taicpu(p).opcode:=A_UXTB
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else
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taicpu(p).opcode:=A_UXTH;
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taicpu(p).loadreg(1, taicpu(p).oper[0]^.reg);
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result := true;
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end
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else if (p.typ=ait_instruction) and
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MatchInstruction(p, [A_AND], [], [PF_None]) and
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(taicpu(p).ops = 3) and
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(taicpu(p).oper[2]^.typ=top_const) and
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((taicpu(p).oper[2]^.val=255) or
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(taicpu(p).oper[2]^.val=65535)) then
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begin
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if taicpu(p).oper[2]^.val=255 then
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taicpu(p).opcode:=A_UXTB
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else
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taicpu(p).opcode:=A_UXTH;
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taicpu(p).ops:=2;
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result := true;
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end
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{else if (p.typ=ait_instruction) and
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MatchInstruction(p, [A_CMP], [C_None], [PF_None]) and
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(taicpu(p).oper[1]^.typ=top_const) and
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(taicpu(p).oper[1]^.val=0) and
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GetNextInstruction(p,hp1) and
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(taicpu(hp1).opcode=A_B) and
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(taicpu(hp1).condition in [C_EQ,C_NE]) then
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begin
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if taicpu(hp1).condition = C_EQ then
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hp2:=taicpu.op_reg_ref(A_CBZ, taicpu(p).oper[0]^.reg, taicpu(hp1).oper[0]^.ref^)
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else
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hp2:=taicpu.op_reg_ref(A_CBNZ, taicpu(p).oper[0]^.reg, taicpu(hp1).oper[0]^.ref^);
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taicpu(hp2).is_jmp := true;
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asml.InsertAfter(hp2, hp1);
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asml.Remove(hp1);
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hp1.Free;
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asml.Remove(p);
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p.Free;
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p := hp2;
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result := true;
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end}
|
||||
else
|
||||
Result := inherited PeepHoleOptPass1Cpu(p);
|
||||
end;
|
||||
|
||||
procedure TCpuThumb2AsmOptimizer.PeepHoleOptPass2;
|
||||
var
|
||||
p,hp1,hp2: tai;
|
||||
l,l2 : longint;
|
||||
condition : tasmcond;
|
||||
hp3: tai;
|
||||
WasLast: boolean;
|
||||
{ UsedRegs, TmpUsedRegs: TRegSet; }
|
||||
|
||||
begin
|
||||
p := BlockStart;
|
||||
{ UsedRegs := []; }
|
||||
while (p <> BlockEnd) Do
|
||||
begin
|
||||
{ UpdateUsedRegs(UsedRegs, tai(p.next)); }
|
||||
case p.Typ Of
|
||||
Ait_Instruction:
|
||||
begin
|
||||
case taicpu(p).opcode Of
|
||||
A_B:
|
||||
if taicpu(p).condition<>C_None then
|
||||
begin
|
||||
{ check for
|
||||
Bxx xxx
|
||||
<several instructions>
|
||||
xxx:
|
||||
}
|
||||
l:=0;
|
||||
GetNextInstruction(p, hp1);
|
||||
while assigned(hp1) and
|
||||
(l<=4) and
|
||||
CanBeCond(hp1) and
|
||||
{ stop on labels }
|
||||
not(hp1.typ=ait_label) do
|
||||
begin
|
||||
inc(l);
|
||||
if MustBeLast(hp1) then
|
||||
begin
|
||||
//hp1:=nil;
|
||||
GetNextInstruction(hp1,hp1);
|
||||
break;
|
||||
end
|
||||
else
|
||||
GetNextInstruction(hp1,hp1);
|
||||
end;
|
||||
if assigned(hp1) then
|
||||
begin
|
||||
if FindLabel(tasmlabel(taicpu(p).oper[0]^.ref^.symbol),hp1) then
|
||||
begin
|
||||
if (l<=4) and (l>0) then
|
||||
begin
|
||||
condition:=inverse_cond(taicpu(p).condition);
|
||||
hp2:=p;
|
||||
GetNextInstruction(p,hp1);
|
||||
p:=hp1;
|
||||
repeat
|
||||
if hp1.typ=ait_instruction then
|
||||
taicpu(hp1).condition:=condition;
|
||||
if MustBeLast(hp1) then
|
||||
begin
|
||||
GetNextInstruction(hp1,hp1);
|
||||
break;
|
||||
end
|
||||
else
|
||||
GetNextInstruction(hp1,hp1);
|
||||
until not(assigned(hp1)) or
|
||||
not(CanBeCond(hp1)) or
|
||||
(hp1.typ=ait_label);
|
||||
{ wait with removing else GetNextInstruction could
|
||||
ignore the label if it was the only usage in the
|
||||
jump moved away }
|
||||
|
||||
asml.InsertAfter(tai_comment.create(strpnew('Collapsed')), hp2);
|
||||
|
||||
DecrementPreceedingIT(asml, hp2);
|
||||
|
||||
case l of
|
||||
1: asml.InsertAfter(taicpu.op_cond(A_IT,condition), hp2);
|
||||
2: asml.InsertAfter(taicpu.op_cond(A_ITT,condition), hp2);
|
||||
3: asml.InsertAfter(taicpu.op_cond(A_ITTT,condition), hp2);
|
||||
4: asml.InsertAfter(taicpu.op_cond(A_ITTTT,condition), hp2);
|
||||
end;
|
||||
|
||||
tasmlabel(taicpu(hp2).oper[0]^.ref^.symbol).decrefs;
|
||||
asml.remove(hp2);
|
||||
hp2.free;
|
||||
continue;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
end;
|
||||
p := tai(p.next)
|
||||
end;
|
||||
end;
|
||||
|
||||
begin
|
||||
|
||||
@ -206,6 +206,10 @@
|
||||
'sel',
|
||||
'setend',
|
||||
'sev',
|
||||
'asr',
|
||||
'lsr',
|
||||
'lsl',
|
||||
'ror',
|
||||
'shadd16',
|
||||
'shadd8',
|
||||
'shasx',
|
||||
@ -270,12 +274,8 @@
|
||||
'wfe',
|
||||
'wfi',
|
||||
'yield',
|
||||
'asr',
|
||||
'lsr',
|
||||
'lsl',
|
||||
'pop',
|
||||
'push',
|
||||
'ror',
|
||||
'sdiv',
|
||||
'udiv',
|
||||
'movt',
|
||||
@ -295,5 +295,7 @@
|
||||
'itett',
|
||||
'itttt',
|
||||
'tbb',
|
||||
'tbh'
|
||||
'tbh',
|
||||
'cbz',
|
||||
'cbnz'
|
||||
);
|
||||
|
||||
@ -295,5 +295,7 @@ attsufNONE,
|
||||
attsufNONE,
|
||||
attsufNONE,
|
||||
attsufNONE,
|
||||
attsufNONE,
|
||||
attsufNONE,
|
||||
attsufNONE
|
||||
);
|
||||
|
||||
@ -618,6 +618,14 @@ reg32,reg32,reg32,reg32 \x16\x00\x80\x90 ARM7
|
||||
|
||||
[SEVcc]
|
||||
|
||||
[ASRcc]
|
||||
|
||||
[LSRcc]
|
||||
|
||||
[LSLcc]
|
||||
|
||||
[RORcc]
|
||||
|
||||
[SHADD16cc]
|
||||
[SHADD8cc]
|
||||
[SHASXcc]
|
||||
@ -702,18 +710,10 @@ reg32,reg32,reg32,reg32 \x16\x00\x80\x90 ARM7
|
||||
|
||||
; Thumb-2
|
||||
|
||||
[ASRcc]
|
||||
|
||||
[LSRcc]
|
||||
|
||||
[LSLcc]
|
||||
|
||||
[POP]
|
||||
|
||||
[PUSH]
|
||||
|
||||
[RORcc]
|
||||
|
||||
[SDIVcc]
|
||||
|
||||
[UDIVcc]
|
||||
@ -752,3 +752,6 @@ reg32,reg32,reg32,reg32 \x16\x00\x80\x90 ARM7
|
||||
|
||||
[TBB]
|
||||
[TBH]
|
||||
|
||||
[CBZ]
|
||||
[CBNZ]
|
||||
@ -206,6 +206,10 @@ A_SBFX,
|
||||
A_SEL,
|
||||
A_SETEND,
|
||||
A_SEV,
|
||||
A_ASR,
|
||||
A_LSR,
|
||||
A_LSL,
|
||||
A_ROR,
|
||||
A_SHADD16,
|
||||
A_SHADD8,
|
||||
A_SHASX,
|
||||
@ -270,12 +274,8 @@ A_UXTH,
|
||||
A_WFE,
|
||||
A_WFI,
|
||||
A_YIELD,
|
||||
A_ASR,
|
||||
A_LSR,
|
||||
A_LSL,
|
||||
A_POP,
|
||||
A_PUSH,
|
||||
A_ROR,
|
||||
A_SDIV,
|
||||
A_UDIV,
|
||||
A_MOVT,
|
||||
@ -295,5 +295,7 @@ A_ITTET,
|
||||
A_ITETT,
|
||||
A_ITTTT,
|
||||
A_TBB,
|
||||
A_TBH
|
||||
A_TBH,
|
||||
A_CBZ,
|
||||
A_CBNZ
|
||||
);
|
||||
|
||||
@ -48,7 +48,7 @@ unit cpubase;
|
||||
TAsmOp= {$i armop.inc}
|
||||
{This is a bit of a hack, because there are more than 256 ARM Assembly Ops
|
||||
But FPC currently can't handle more than 256 elements in a set.}
|
||||
TCommonAsmOps = Set of A_None .. A_UQSADA8;
|
||||
TCommonAsmOps = Set of A_None .. A_UQSAX;
|
||||
|
||||
{ This should define the array of instructions as string }
|
||||
op2strtable=array[tasmop] of string[11];
|
||||
|
||||
@ -70,10 +70,17 @@ unit rgcpu;
|
||||
procedure trgintcputhumb2.add_cpu_interferences(p: tai);
|
||||
var
|
||||
r : tregister;
|
||||
hr : longint;
|
||||
begin
|
||||
if p.typ=ait_instruction then
|
||||
begin
|
||||
case taicpu(p).opcode of
|
||||
A_CBNZ,
|
||||
A_CBZ:
|
||||
begin
|
||||
for hr := RS_R8 to RS_R15 do
|
||||
add_edge(getsupreg(taicpu(p).oper[0]^.reg), hr);
|
||||
end;
|
||||
A_ADD:
|
||||
begin
|
||||
if taicpu(p).ops = 3 then
|
||||
|
||||
Loading…
Reference in New Issue
Block a user