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9ec9b44784
Create preliminary Thumb-2 PeepHoleOptPass2 code, hacked together from the ARM mode code Added a number of simple size optimizations for common Thumb-2 instructions git-svn-id: branches/laksen/arm-embedded@22590 -
526 lines
19 KiB
ObjectPascal
526 lines
19 KiB
ObjectPascal
{
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Copyright (c) 1998-2003 by Florian Klaempfl
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This unit implements the arm specific class for the register
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allocator
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit rgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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aasmbase,aasmtai,aasmdata,aasmcpu,
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cgbase,cgutils,
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cpubase,
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rgobj;
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type
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trgcpu = class(trgobj)
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private
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procedure spilling_create_load_store(list: TAsmList; pos: tai; const spilltemp:treference;tempreg:tregister; is_store: boolean);
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public
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procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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procedure add_constraints(reg:tregister);override;
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function get_spill_subreg(r:tregister) : tsubregister;override;
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end;
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trgcputhumb2 = class(trgobj)
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private
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procedure SplitITBlock(list:TAsmList;pos:tai);
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public
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procedure do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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procedure do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);override;
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end;
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trgintcputhumb2 = class(trgcputhumb2)
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procedure add_cpu_interferences(p : tai);override;
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end;
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trgintcpu = class(trgcpu)
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procedure add_cpu_interferences(p : tai);override;
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end;
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implementation
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uses
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verbose, cutils,globtype,globals,cpuinfo,
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cgobj,
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procinfo;
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procedure trgintcputhumb2.add_cpu_interferences(p: tai);
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var
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r : tregister;
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hr : longint;
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begin
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if p.typ=ait_instruction then
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begin
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case taicpu(p).opcode of
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A_CBNZ,
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A_CBZ:
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begin
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for hr := RS_R8 to RS_R15 do
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add_edge(getsupreg(taicpu(p).oper[0]^.reg), hr);
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end;
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A_ADD:
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begin
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if taicpu(p).ops = 3 then
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begin
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if (taicpu(p).oper[0]^.typ = top_reg) and
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(taicpu(p).oper[1]^.typ = top_reg) and
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(taicpu(p).oper[2]^.typ in [top_reg, top_shifterop]) then
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begin
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{ if d == 13 || (d == 15 && S == ‘0’) || n == 15 || m IN [13,15] then UNPREDICTABLE; }
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add_edge(getsupreg(taicpu(p).oper[0]^.reg), RS_R13);
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if taicpu(p).oppostfix <> PF_S then
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add_edge(getsupreg(taicpu(p).oper[0]^.reg), RS_R15);
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add_edge(getsupreg(taicpu(p).oper[1]^.reg), RS_R15);
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if (taicpu(p).oper[2]^.typ = top_shifterop) and
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(taicpu(p).oper[2]^.shifterop^.rs <> NR_NO) then
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begin
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add_edge(getsupreg(taicpu(p).oper[2]^.shifterop^.rs), RS_R13);
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add_edge(getsupreg(taicpu(p).oper[2]^.shifterop^.rs), RS_R15);
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end
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else if (taicpu(p).oper[2]^.typ = top_reg) then
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begin
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add_edge(getsupreg(taicpu(p).oper[2]^.reg), RS_R13);
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add_edge(getsupreg(taicpu(p).oper[2]^.reg), RS_R15);
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end;
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end;
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end;
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end;
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A_LDRB,
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A_STRB,
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A_STR,
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A_LDR,
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A_LDRH,
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A_STRH,
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A_LDRSB,
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A_LDRSH,
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A_LDRD,
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A_STRD:
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{ don't mix up the framepointer and stackpointer with pre/post indexed operations }
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if (taicpu(p).oper[1]^.typ=top_ref) and
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(taicpu(p).oper[1]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) then
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begin
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add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(current_procinfo.framepointer));
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{ FIXME: temp variable r is needed here to avoid Internal error 20060521 }
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{ while compiling the compiler. }
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r:=NR_STACK_POINTER_REG;
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if current_procinfo.framepointer<>r then
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add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(r));
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end;
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end;
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end;
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end;
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procedure trgcpu.spilling_create_load_store(list: TAsmList; pos: tai; const spilltemp:treference;tempreg:tregister; is_store: boolean);
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var
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tmpref : treference;
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helplist : TAsmList;
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l : tasmlabel;
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hreg : tregister;
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immshift: byte;
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a: aint;
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begin
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helplist:=TAsmList.create;
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{ load consts entry }
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if getregtype(tempreg)=R_INTREGISTER then
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hreg:=getregisterinline(helplist,[R_SUBWHOLE])
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else
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hreg:=cg.getintregister(helplist,OS_ADDR);
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{ Lets remove the bits we can fold in later and check if the result can be easily with an add or sub }
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a:=abs(spilltemp.offset);
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if is_shifter_const(a and not($FFF), immshift) then
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if spilltemp.offset > 0 then
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begin
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{$ifdef DEBUG_SPILLING}
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helplist.concat(tai_comment.create(strpnew('Spilling: Use ADD to fix spill offset')));
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{$endif}
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helplist.concat(taicpu.op_reg_reg_const(A_ADD, hreg, current_procinfo.framepointer,
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a and not($FFF)));
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reference_reset_base(tmpref, hreg, a and $FFF, sizeof(aint));
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end
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else
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begin
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{$ifdef DEBUG_SPILLING}
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helplist.concat(tai_comment.create(strpnew('Spilling: Use SUB to fix spill offset')));
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{$endif}
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helplist.concat(taicpu.op_reg_reg_const(A_SUB, hreg, current_procinfo.framepointer,
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a and not($FFF)));
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reference_reset_base(tmpref, hreg, -(a and $FFF), sizeof(aint));
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end
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else
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begin
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{$ifdef DEBUG_SPILLING}
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helplist.concat(tai_comment.create(strpnew('Spilling: Use a_load_const_reg to fix spill offset')));
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{$endif}
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cg.a_load_const_reg(helplist,OS_ADDR,spilltemp.offset,hreg);
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reference_reset_base(tmpref,current_procinfo.framepointer,0,sizeof(aint));
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tmpref.index:=hreg;
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end;
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if spilltemp.index<>NR_NO then
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internalerror(200401263);
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if is_store then
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helplist.concat(spilling_create_store(tempreg,tmpref))
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else
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helplist.concat(spilling_create_load(tmpref,tempreg));
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if getregtype(tempreg)=R_INTREGISTER then
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ungetregisterinline(helplist,hreg);
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list.insertlistafter(pos,helplist);
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helplist.free;
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end;
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procedure trgcpu.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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begin
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{ don't load spilled register between
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mov lr,pc
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mov pc,r4
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but befure the mov lr,pc
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}
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if assigned(pos.previous) and
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(pos.typ=ait_instruction) and
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(taicpu(pos).opcode=A_MOV) and
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(taicpu(pos).oper[0]^.typ=top_reg) and
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(taicpu(pos).oper[0]^.reg=NR_R14) and
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(taicpu(pos).oper[1]^.typ=top_reg) and
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(taicpu(pos).oper[1]^.reg=NR_PC) then
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pos:=tai(pos.previous);
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if abs(spilltemp.offset)>4095 then
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spilling_create_load_store(list, pos, spilltemp, tempreg, false)
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else
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inherited do_spill_read(list,pos,spilltemp,tempreg);
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end;
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procedure trgcpu.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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begin
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if abs(spilltemp.offset)>4095 then
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spilling_create_load_store(list, pos, spilltemp, tempreg, true)
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else
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inherited do_spill_written(list,pos,spilltemp,tempreg);
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end;
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procedure trgcpu.add_constraints(reg:tregister);
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var
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supreg,i : Tsuperregister;
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begin
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case getsubreg(reg) of
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{ Let 32bit floats conflict with all double precision regs > 15
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(since these don't have 32 bit equivalents) }
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R_SUBFS:
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begin
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supreg:=getsupreg(reg);
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for i:=RS_D16 to RS_D31 do
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add_edge(supreg,i);
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end;
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end;
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end;
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function trgcpu.get_spill_subreg(r:tregister) : tsubregister;
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begin
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if (getregtype(r)<>R_MMREGISTER) then
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result:=defaultsub
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else
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result:=getsubreg(r);
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end;
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function IsIT(op: TAsmOp) : boolean;
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begin
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case op of
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A_IT,
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A_ITE, A_ITT,
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A_ITEE, A_ITTE, A_ITET, A_ITTT,
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A_ITEEE, A_ITTEE, A_ITETE, A_ITTTE,
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A_ITEET, A_ITTET, A_ITETT, A_ITTTT:
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result:=true;
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else
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result:=false;
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end;
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end;
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function GetITLevels(op: TAsmOp) : longint;
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begin
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case op of
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A_IT:
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result:=1;
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A_ITE, A_ITT:
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result:=2;
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A_ITEE, A_ITTE, A_ITET, A_ITTT:
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result:=3;
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A_ITEEE, A_ITTEE, A_ITETE, A_ITTTE,
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A_ITEET, A_ITTET, A_ITETT, A_ITTTT:
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result:=4;
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else
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result:=0;
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end;
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end;
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function GetITRemainderOp(originalOp:TAsmOp;remLevels:longint;var newOp: TAsmOp;var NeedsCondSwap:boolean) : TAsmOp;
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const
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remOps : array[1..3] of array[A_ITE..A_ITTTT] of TAsmOp = (
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(A_IT,A_IT, A_IT,A_IT,A_IT,A_IT, A_IT,A_IT,A_IT,A_IT,A_IT,A_IT,A_IT,A_IT),
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(A_NONE,A_NONE, A_ITT,A_ITE,A_ITE,A_ITT, A_ITT,A_ITT,A_ITE,A_ITE,A_ITE,A_ITE,A_ITT,A_ITT),
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(A_NONE,A_NONE, A_NONE,A_NONE,A_NONE,A_NONE, A_ITTT,A_ITEE,A_ITET,A_ITTE,A_ITTE,A_ITET,A_ITEE,A_ITTT));
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newOps : array[1..3] of array[A_ITE..A_ITTTT] of TAsmOp = (
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(A_IT,A_IT, A_ITE,A_ITT,A_ITE,A_ITT, A_ITEE,A_ITTE,A_ITET,A_ITTT,A_ITEE,A_ITTE,A_ITET,A_ITTT),
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(A_NONE,A_NONE, A_IT,A_IT,A_IT,A_IT, A_ITE,A_ITT,A_ITE,A_ITT,A_ITE,A_ITT,A_ITE,A_ITT),
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(A_NONE,A_NONE, A_NONE,A_NONE,A_NONE,A_NONE, A_IT,A_IT,A_IT,A_IT,A_IT,A_IT,A_IT,A_IT));
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needsSwap: array[1..3] of array[A_ITE..A_ITTTT] of Boolean = (
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(true ,false, true ,true ,false,false, true ,true ,true ,true ,false,false,false,false),
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(false,false, true ,false,true ,false, true ,true ,false,false,true ,true ,false,false),
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(false,false, false,false,false,false, true ,false,true ,false,true ,false,true ,false));
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begin
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result:=remOps[remLevels][originalOp];
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newOp:=newOps[remLevels][originalOp];
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NeedsCondSwap:=needsSwap[remLevels][originalOp];
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end;
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procedure trgcputhumb2.SplitITBlock(list: TAsmList; pos: tai);
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var
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hp : tai;
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level,itLevel : LongInt;
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remOp,newOp : TAsmOp;
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needsSwap : boolean;
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begin
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hp:=pos;
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level := 0;
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while assigned(hp) do
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begin
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if IsIT(taicpu(hp).opcode) then
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break
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else if hp.typ=ait_instruction then
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inc(level);
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hp:=tai(hp.Previous);
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end;
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if not assigned(hp) then
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internalerror(2012100801); // We are supposed to have found the ITxxx instruction here
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if (hp.typ<>ait_instruction) or
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(not IsIT(taicpu(hp).opcode)) then
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internalerror(2012100802); // Sanity check
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itLevel := GetITLevels(taicpu(hp).opcode);
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if level=itLevel then
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exit; // pos was the last instruction in the IT block anyway
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remOp:=GetITRemainderOp(taicpu(hp).opcode,itLevel-level,newOp,needsSwap);
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if (remOp=A_NONE) or
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(newOp=A_NONE) then
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Internalerror(2012100803);
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taicpu(hp).opcode:=newOp;
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if needsSwap then
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list.InsertAfter(taicpu.op_cond(remOp,inverse_cond(taicpu(hp).oper[0]^.cc)), pos)
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else
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list.InsertAfter(taicpu.op_cond(remOp,taicpu(hp).oper[0]^.cc), pos);
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end;
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procedure trgcputhumb2.do_spill_read(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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var
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tmpref : treference;
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helplist : TAsmList;
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l : tasmlabel;
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hreg : tregister;
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begin
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{ don't load spilled register between
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mov lr,pc
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mov pc,r4
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but befure the mov lr,pc
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}
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if assigned(pos.previous) and
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(pos.typ=ait_instruction) and
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(taicpu(pos).opcode=A_MOV) and
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(taicpu(pos).oper[0]^.typ=top_reg) and
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(taicpu(pos).oper[0]^.reg=NR_R14) and
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(taicpu(pos).oper[1]^.typ=top_reg) and
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(taicpu(pos).oper[1]^.reg=NR_PC) then
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pos:=tai(pos.previous);
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if (pos.typ=ait_instruction) and
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(taicpu(pos).condition<>C_None) and
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(taicpu(pos).opcode<>A_B) then
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SplitITBlock(list, pos)
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else if (pos.typ=ait_instruction) and
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IsIT(taicpu(pos).opcode) then
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begin
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if not assigned(pos.Previous) then
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list.InsertBefore(tai_comment.Create('Dummy'), pos);
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pos:=tai(pos.Previous);
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end;
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if (spilltemp.offset>4095) or (spilltemp.offset<-255) then
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begin
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helplist:=TAsmList.create;
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reference_reset(tmpref,sizeof(aint));
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{ create consts entry }
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current_asmdata.getjumplabel(l);
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cg.a_label(current_procinfo.aktlocaldata,l);
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tmpref.symboldata:=current_procinfo.aktlocaldata.last;
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current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(spilltemp.offset));
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{ load consts entry }
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if getregtype(tempreg)=R_INTREGISTER then
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hreg:=getregisterinline(helplist,[R_SUBWHOLE])
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else
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hreg:=cg.getintregister(helplist,OS_ADDR);
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tmpref.symbol:=l;
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tmpref.base:=NR_R15;
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helplist.concat(taicpu.op_reg_ref(A_LDR,hreg,tmpref));
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reference_reset_base(tmpref,current_procinfo.framepointer,0,sizeof(aint));
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tmpref.index:=hreg;
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if spilltemp.index<>NR_NO then
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internalerror(200401263);
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helplist.concat(spilling_create_load(tmpref,tempreg));
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if getregtype(tempreg)=R_INTREGISTER then
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ungetregisterinline(helplist,hreg);
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list.insertlistafter(pos,helplist);
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helplist.free;
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end
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else
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inherited do_spill_read(list,pos,spilltemp,tempreg);
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end;
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procedure trgcputhumb2.do_spill_written(list:TAsmList;pos:tai;const spilltemp:treference;tempreg:tregister);
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var
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tmpref : treference;
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helplist : TAsmList;
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l : tasmlabel;
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hreg : tregister;
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begin
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if (pos.typ=ait_instruction) and
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(taicpu(pos).condition<>C_None) and
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(taicpu(pos).opcode<>A_B) then
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SplitITBlock(list, pos)
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else if (pos.typ=ait_instruction) and
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IsIT(taicpu(pos).opcode) then
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begin
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if not assigned(pos.Previous) then
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list.InsertBefore(tai_comment.Create('Dummy'), pos);
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pos:=tai(pos.Previous);
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end;
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if (spilltemp.offset>4095) or (spilltemp.offset<-255) then
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begin
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helplist:=TAsmList.create;
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reference_reset(tmpref,sizeof(aint));
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{ create consts entry }
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current_asmdata.getjumplabel(l);
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cg.a_label(current_procinfo.aktlocaldata,l);
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tmpref.symboldata:=current_procinfo.aktlocaldata.last;
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current_procinfo.aktlocaldata.concat(tai_const.Create_32bit(spilltemp.offset));
|
||
|
||
{ load consts entry }
|
||
if getregtype(tempreg)=R_INTREGISTER then
|
||
hreg:=getregisterinline(helplist,[R_SUBWHOLE])
|
||
else
|
||
hreg:=cg.getintregister(helplist,OS_ADDR);
|
||
tmpref.symbol:=l;
|
||
tmpref.base:=NR_R15;
|
||
helplist.concat(taicpu.op_reg_ref(A_LDR,hreg,tmpref));
|
||
|
||
if spilltemp.index<>NR_NO then
|
||
internalerror(200401263);
|
||
|
||
reference_reset_base(tmpref,current_procinfo.framepointer,0,sizeof(pint));
|
||
tmpref.index:=hreg;
|
||
|
||
helplist.concat(spilling_create_store(tempreg,tmpref));
|
||
|
||
if getregtype(tempreg)=R_INTREGISTER then
|
||
ungetregisterinline(helplist,hreg);
|
||
|
||
list.insertlistafter(pos,helplist);
|
||
helplist.free;
|
||
end
|
||
else
|
||
inherited do_spill_written(list,pos,spilltemp,tempreg);
|
||
end;
|
||
|
||
|
||
procedure trgintcpu.add_cpu_interferences(p : tai);
|
||
var
|
||
r : tregister;
|
||
begin
|
||
if p.typ=ait_instruction then
|
||
begin
|
||
case taicpu(p).opcode of
|
||
A_MLA,
|
||
A_MUL:
|
||
if current_settings.cputype<cpu_armv6 then
|
||
add_edge(getsupreg(taicpu(p).oper[0]^.reg),getsupreg(taicpu(p).oper[1]^.reg));
|
||
A_UMULL,
|
||
A_UMLAL,
|
||
A_SMULL,
|
||
A_SMLAL:
|
||
begin
|
||
add_edge(getsupreg(taicpu(p).oper[0]^.reg),getsupreg(taicpu(p).oper[1]^.reg));
|
||
add_edge(getsupreg(taicpu(p).oper[1]^.reg),getsupreg(taicpu(p).oper[2]^.reg));
|
||
add_edge(getsupreg(taicpu(p).oper[0]^.reg),getsupreg(taicpu(p).oper[2]^.reg));
|
||
end;
|
||
A_LDRB,
|
||
A_STRB,
|
||
A_STR,
|
||
A_LDR,
|
||
A_LDRH,
|
||
A_STRH:
|
||
{ don't mix up the framepointer and stackpointer with pre/post indexed operations }
|
||
if (taicpu(p).oper[1]^.typ=top_ref) and
|
||
(taicpu(p).oper[1]^.ref^.addressmode in [AM_PREINDEXED,AM_POSTINDEXED]) then
|
||
begin
|
||
add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(current_procinfo.framepointer));
|
||
{ FIXME: temp variable r is needed here to avoid Internal error 20060521 }
|
||
{ while compiling the compiler. }
|
||
r:=NR_STACK_POINTER_REG;
|
||
if current_procinfo.framepointer<>r then
|
||
add_edge(getsupreg(taicpu(p).oper[1]^.ref^.base),getsupreg(r));
|
||
end;
|
||
end;
|
||
end;
|
||
end;
|
||
|
||
|
||
end.
|