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* x86: New CMP optimisation that mimics some of the CMOV optimisations and removes unnecessary conditions.
This commit is contained in:
J. Gareth "Curious Kit" Moreton
FPK
parent
bab60d819f
commit
b108608b29
@ -7518,109 +7518,140 @@ unit aoptx86;
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GetNextInstruction(p_jump, p_jump);
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GetNextInstruction(p_jump, p_jump);
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end;
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end;
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{
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if (
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Try to optimise the following:
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{ Don't call GetNextInstruction again if we already have it }
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cmp $x,### ($x and $y can be registers or constants)
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je @lbl1 (only reference)
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cmp $y,### (### are identical)
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@Lbl:
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sete %reg1
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Change to:
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cmp $x,###
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sete %reg2 (allocate new %reg2)
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cmp $y,###
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sete %reg1
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orb %reg2,%reg1
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(dealloc %reg2)
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This adds an instruction (so don't perform under -Os), but it removes
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a conditional branch.
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}
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if not (cs_opt_size in current_settings.optimizerswitches) and
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(
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(hp1 = p_jump) or
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(hp1 = p_jump) or
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GetNextInstruction(p, hp1)
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GetNextInstruction(p, hp1)
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) and
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) and
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MatchInstruction(hp1, A_Jcc, []) and
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MatchInstruction(hp1, A_Jcc, []) and
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IsJumpToLabel(taicpu(hp1)) and
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IsJumpToLabel(taicpu(hp1)) and
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(taicpu(hp1).condition in [C_E, C_Z]) and
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(taicpu(hp1).condition in [C_E, C_Z, C_NE, C_NZ]) and
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GetNextInstruction(hp1, hp2) and
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GetNextInstruction(hp1, hp2) then
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MatchInstruction(hp2, A_CMP, A_TEST, [taicpu(p).opsize]) and
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MatchOperand(taicpu(p).oper[1]^, taicpu(hp2).oper[1]^) and
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{ The first operand of CMP instructions can only be a register or
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immediate anyway, so no need to check }
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GetNextInstruction(hp2, p_label) and
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(
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(p_label.typ = ait_label) or
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(
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{ Sometimes there's a zero-distance jump before the label, so deal with it here
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to potentially cut down on the iterations of Pass 1 }
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MatchInstruction(p_label, A_Jcc, []) and
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IsJumpToLabel(taicpu(p_label)) and
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{ Use p_dist to hold the jump briefly }
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SetAndTest(p_label, p_dist) and
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GetNextInstruction(p_dist, p_label) and
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(p_label.typ = ait_label) and
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(tai_label(p_label).labsym.getrefs >= 2) and
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(JumpTargetOp(taicpu(p_dist))^.ref^.symbol = tai_label(p_label).labsym) and
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{ We might as well collapse the jump now }
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CollapseZeroDistJump(p_dist, tai_label(p_label).labsym)
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)
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) and
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(tai_label(p_label).labsym.getrefs = 1) and
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(JumpTargetOp(taicpu(hp1))^.ref^.symbol = tai_label(p_label).labsym) and
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GetNextInstruction(p_label, p_dist) and
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MatchInstruction(p_dist, A_SETcc, []) and
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(taicpu(p_dist).condition in [C_E, C_Z]) and
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(taicpu(p_dist).oper[0]^.typ = top_reg) and
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{ Get the instruction after the SETcc instruction so we can
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allocate a new register over the entire range }
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GetNextInstruction(p_dist, hp1_dist) then
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begin
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begin
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TransferUsedRegs(TmpUsedRegs);
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{
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UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
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cmp x, y (or "cmp y, x")
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UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
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je @lbl
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UpdateUsedRegs(TmpUsedRegs, tai(p_label.Next));
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mov x, y
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// UpdateUsedRegs(TmpUsedRegs, tai(p_dist.Next));
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@lbl:
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(x and y can be constants, registers or references)
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{ RegUsedAfterInstruction modifies TmpUsedRegs }
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Change to:
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if not RegUsedAfterInstruction(NR_DEFAULTFLAGS, p_dist, TmpUsedRegs) then
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mov x, y (x and y will always be equal in the end)
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@lbl: (may beceome a dead label)
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Also:
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cmp x, y (or "cmp y, x")
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jne @lbl
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mov x, y
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@lbl:
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(x and y can be constants, registers or references)
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Change to:
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Absolutely nothing! (Except @lbl if it's still live)
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}
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if MatchInstruction(hp2, A_MOV, [taicpu(p).opsize]) and
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(
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(
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MatchOperand(taicpu(p).oper[0]^, taicpu(hp2).oper[0]^) and
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MatchOperand(taicpu(p).oper[1]^, taicpu(hp2).oper[1]^)
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) or (
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MatchOperand(taicpu(p).oper[0]^, taicpu(hp2).oper[1]^) and
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MatchOperand(taicpu(p).oper[1]^, taicpu(hp2).oper[0]^)
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)
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) and
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GetNextInstruction(hp2, hp1_label) and
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SkipAligns(hp1_label, hp1_label) and
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(hp1_label.typ = ait_label) and
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(tai_label(hp1_label).labsym = taicpu(hp1).oper[0]^.ref^.symbol) then
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begin
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begin
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{ Register can appear in p if it's not used afterwards, so only
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tai_label(hp1_label).labsym.DecRefs;
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allocate between hp1 and hp1_dist }
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if (taicpu(hp1).condition in [C_NE, C_NZ]) then
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NewReg := GetIntRegisterBetween(R_SUBL, TmpUsedRegs, hp1, p_dist);
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if NewReg <> NR_NO then
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begin
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begin
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DebugMsg(SPeepholeOptimization + 'CMP/JE/CMP/@Lbl/SETE -> CMP/SETE/CMP/SETE/OR, removing conditional branch', p);
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DebugMsg(SPeepholeOptimization + 'CMP/JNE/MOV/@Lbl -> NOP, since the MOV is only executed if the operands are equal (CmpJneMov2Nop)', p);
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RemoveInstruction(hp2);
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hp2 := hp1_label; { So RemoveCurrentp below can be set to something valid }
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end
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else
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DebugMsg(SPeepholeOptimization + 'CMP/JE/MOV/@Lbl -> MOV, since the MOV is only executed if the operands aren''t equal (CmpJeMov2Mov)', p);
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{ Change the jump instruction into a SETcc instruction }
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RemoveInstruction(hp1);
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taicpu(hp1).opcode := A_SETcc;
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RemoveCurrentp(p, hp2);
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taicpu(hp1).opsize := S_B;
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Result := True;
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taicpu(hp1).loadreg(0, NewReg);
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Exit;
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end;
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{ This is now a dead label }
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{
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tai_label(p_label).labsym.decrefs;
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Try to optimise the following:
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cmp $x,### ($x and $y can be registers or constants)
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je @lbl1 (only reference)
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cmp $y,### (### are identical)
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@Lbl:
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sete %reg1
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{ Prefer adding before the next instruction so the FLAGS
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Change to:
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register is deallocated first }
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cmp $x,###
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hp2 := taicpu.op_reg_reg(A_OR, S_B, NewReg, taicpu(p_dist).oper[0]^.reg);
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sete %reg2 (allocate new %reg2)
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taicpu(hp2).fileinfo := taicpu(p_dist).fileinfo;
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cmp $y,###
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sete %reg1
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orb %reg2,%reg1
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(dealloc %reg2)
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AsmL.InsertBefore(
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This adds an instruction (so don't perform under -Os), but it removes
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hp2,
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a conditional branch.
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hp1_dist
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}
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);
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if not (cs_opt_size in current_settings.optimizerswitches) and
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MatchInstruction(hp2, A_CMP, A_TEST, [taicpu(p).opsize]) and
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MatchOperand(taicpu(p).oper[1]^, taicpu(hp2).oper[1]^) and
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{ The first operand of CMP instructions can only be a register or
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immediate anyway, so no need to check }
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GetNextInstruction(hp2, p_label) and
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(p_label.typ = ait_label) and
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(tai_label(p_label).labsym.getrefs = 1) and
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(JumpTargetOp(taicpu(hp1))^.ref^.symbol = tai_label(p_label).labsym) and
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GetNextInstruction(p_label, p_dist) and
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MatchInstruction(p_dist, A_SETcc, []) and
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(taicpu(p_dist).condition in [C_E, C_Z]) and
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(taicpu(p_dist).oper[0]^.typ = top_reg) then
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begin
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TransferUsedRegs(TmpUsedRegs);
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UpdateUsedRegs(TmpUsedRegs, tai(hp1.Next));
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UpdateUsedRegs(TmpUsedRegs, tai(hp2.Next));
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UpdateUsedRegs(TmpUsedRegs, tai(p_label.Next));
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UpdateUsedRegs(TmpUsedRegs, tai(p_dist.Next));
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{ Make sure the new register is in use over the new instruction
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if not RegInUsedRegs(NR_DEFAULTFLAGS, TmpUsedRegs) and
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(long-winded, but things work best when the FLAGS register
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{ Get the instruction after the SETcc instruction so we can
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is not allocated here) }
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allocate a new register over the entire range }
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AllocRegBetween(NewReg, p_dist, hp2, TmpUsedRegs);
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GetNextInstruction(p_dist, hp1_dist) then
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begin
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{ Register can appear in p if it's not used afterwards, so only
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allocate between hp1 and hp1_dist }
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NewReg := GetIntRegisterBetween(R_SUBL, TmpUsedRegs, hp1, hp1_dist);
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if NewReg <> NR_NO then
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begin
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DebugMsg(SPeepholeOptimization + 'CMP/JE/CMP/@Lbl/SETE -> CMP/SETE/CMP/SETE/OR, removing conditional branch', p);
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Result := True;
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{ Change the jump instruction into a SETcc instruction }
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{ Don't exit yet, as p wasn't changed and hp1, while
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taicpu(hp1).opcode := A_SETcc;
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modified, is still intact and might be optimised by the
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taicpu(hp1).opsize := S_B;
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SETcc optimisation below }
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taicpu(hp1).loadreg(0, NewReg);
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{ This is now a dead label }
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tai_label(p_label).labsym.decrefs;
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{ Prefer adding before the next instruction so the FLAGS
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register is deallicated first }
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AsmL.InsertBefore(
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taicpu.op_reg_reg(A_OR, S_B, NewReg, taicpu(p_dist).oper[0]^.reg),
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hp1_dist
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);
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Result := True;
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{ Don't exit yet, as p wasn't changed and hp1, while
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modified, is still intact and might be optimised by the
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SETcc optimisation below }
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end;
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end;
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end;
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end;
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end;
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end;
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end;
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@ -8733,8 +8764,8 @@ unit aoptx86;
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{ The instruction can be safely moved }
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{ The instruction can be safely moved }
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asml.Remove(hp1);
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asml.Remove(hp1);
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{ Try to insert before the FLAGS register is allocated, so "mov $0,%reg"
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{ Try to insert after the last instructions where the FLAGS register is not
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can be optimised into "xor %reg,%reg" later }
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yet in use, so "mov $0,%reg" can be optimised into "xor %reg,%reg" later }
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if SetAndTest(FindRegAllocBackward(NR_DEFAULTFLAGS, tai(p.Previous)), hp2) then
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if SetAndTest(FindRegAllocBackward(NR_DEFAULTFLAGS, tai(p.Previous)), hp2) then
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asml.InsertBefore(hp1, hp2)
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asml.InsertBefore(hp1, hp2)
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@ -8750,9 +8781,9 @@ unit aoptx86;
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asml.InsertAfter(hp1, hp2)
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asml.InsertAfter(hp1, hp2)
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else
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else
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{ Note, if p.Previous is nil (even if it should logically never be the
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{ Note, if p.Previous is nil (even if it should logically never be the
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case), FindRegAllocBackward immediately exits with False and so we
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case), FindRegAllocBackward immediately exits with False and so we
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safely land here (we can't just pass p because FindRegAllocBackward
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safely land here (we can't just pass p because FindRegAllocBackward
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immediately exits on an instruction). [Kit] }
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immediately exits on an instruction). [Kit] }
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asml.InsertBefore(hp1, p);
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asml.InsertBefore(hp1, p);
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DebugMsg(SPeepholeOptimization + 'Swapped ' + debug_op2str(taicpu(p).opcode) + ' and ' + debug_op2str(taicpu(hp1).opcode) + ' instructions to improve optimisation potential', hp1);
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DebugMsg(SPeepholeOptimization + 'Swapped ' + debug_op2str(taicpu(p).opcode) + ' and ' + debug_op2str(taicpu(hp1).opcode) + ' instructions to improve optimisation potential', hp1);
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