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+ RiscV32: use sext.b if available

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florian 2025-02-24 23:05:49 +01:00
parent eb74850d7c
commit b2f5f6ac7d
1 changed files with 2 additions and 0 deletions
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compiler/riscv32/cgcpu.pas
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@ -125,6 +125,8 @@ unit cgcpu;
list.concat(ai);
rg[R_INTREGISTER].add_move_instruction(ai);
end
else if (CPURV_HAS_ZBB in cpu_capabilities[current_settings.cputype]) and (tcgsize2unsigned[tosize]=OS_32) and (fromsize=OS_S8) then
list.Concat(taicpu.op_reg_reg(A_SEXT_B,reg2,reg1))
else if (tcgsize2unsigned[tosize]=OS_32) and (fromsize=OS_8) then
list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
else if (tosize=OS_8) and (fromsize<>OS_8) then