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* More complete fix for bug #10515. Thanks to Jonas for suggestion.

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* Fixed warnings in tcnvint6.pp

git-svn-id: trunk@10765 -
This commit is contained in:
yury 2008-04-23 08:22:27 +00:00
parent 1810451767
commit b9431c876e
3 changed files with 20 additions and 13 deletions
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17
compiler/arm/cgcpu.pas
View File

@ -106,6 +106,11 @@ unit cgcpu;
function handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference; function handle_load_store(list:TAsmList;op: tasmop;oppostfix : toppostfix;reg:tregister;ref: treference):treference;
procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override; procedure g_intf_wrapper(list: TAsmList; procdef: tprocdef; const labelname: string; ioffset: longint);override;
private
{ clear out potential overflow bits from 8 or 16 bit operations }
{ the upper 24/16 bits of a register after an operation }
procedure maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
end; end;
tcg64farm = class(tcg64f32) tcg64farm = class(tcg64f32)
@ -476,6 +481,7 @@ unit cgcpu;
a_op_reg_reg_reg_checkoverflow(list,op,size,tmpreg,src,dst,setflags,ovloc); a_op_reg_reg_reg_checkoverflow(list,op,size,tmpreg,src,dst,setflags,ovloc);
end; end;
end; end;
maybeadjustresult(list,op,size,dst);
end; end;
@ -571,6 +577,7 @@ unit cgcpu;
taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S)) taicpu.op_reg_reg_reg(op_reg_reg_opcg2asmop[op],dst,src2,src1),toppostfix(ord(cgsetflags or setflags)*ord(PF_S))
)); ));
end; end;
maybeadjustresult(list,op,size,dst);
end; end;
@ -1964,6 +1971,16 @@ unit cgcpu;
end; end;
procedure tcgarm.maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
const
overflowops = [OP_MUL,OP_SHL,OP_ADD,OP_SUB,OP_NOT,OP_NEG];
begin
if (op in overflowops) and
(size in [OS_8,OS_S8,OS_16,OS_S16]) then
a_load_reg_reg(list,OS_32,size,dst,dst);
end;
procedure tcg64farm.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64); procedure tcg64farm.a_op64_reg_reg(list : TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst : tregister64);
begin begin
case op of case op of

10
compiler/arm/narminl.pas
View File

@ -49,7 +49,6 @@ interface
procedure second_sin_real; override; procedure second_sin_real; override;
} }
procedure second_prefetch; override; procedure second_prefetch; override;
procedure second_incdec; override;
private private
procedure load_fpu_location; procedure load_fpu_location;
end; end;
@ -225,15 +224,6 @@ implementation
end; end;
procedure tarminlinenode.second_incdec;
begin
inherited second_incdec;
{ Strip result if inc/dec is performed in register on value less than 32-bit }
with tcallparanode(left).left.location do
if (loc in [LOC_REGISTER,LOC_CREGISTER]) and (tcgsize2size[size]<sizeof(aint)) then
cg.a_load_reg_reg(current_asmdata.CurrAsmList, size, OS_32, register, register)
end;
begin begin
cinlinenode:=tarminlinenode; cinlinenode:=tarminlinenode;
end. end.

6
tests/test/cg/tcnvint6.pp
View File

@ -11,7 +11,7 @@ var
c,c2: cardinal; c,c2: cardinal;
shi,shi2: shortint; shi,shi2: shortint;
si,si2: smallint; si,si2: smallint;
i64,i642: int64; i64: int64;
begin begin
b:=$ff; b:=$ff;
Inc(b,$ff); Inc(b,$ff);
@ -83,7 +83,7 @@ begin
if i64<>$fffffffe then if i64<>$fffffffe then
error(33); error(33);
{$ifdef FPC} {$ifdef FPC}
if qword(shi)<>$fffffffffffffffe then if qword(shi)<>qword($fffffffffffffffe) then
error(34); error(34);
{$endif FPC} {$endif FPC}
shi2:=-2; shi2:=-2;
@ -100,7 +100,7 @@ begin
if i64<>$fffffffe then if i64<>$fffffffe then
halt(43); halt(43);
{$ifdef FPC} {$ifdef FPC}
if qword(si)<>$fffffffffffffffe then if qword(si)<>qword($fffffffffffffffe) then
error(44); error(44);
{$endif FPC} {$endif FPC}
si2:=-2; si2:=-2;