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https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-08-16 19:59:18 +02:00
Changed order in stack unravelling RTL code, to match the most common cases.
Fixed unsigned conditions for branch conditions. Added some additional const loading cases. Changed the temporary register used during calls because it could otherwise clash with the argument passing registers. git-svn-id: branches/laksen/riscv_new@39492 -
This commit is contained in:
Jeppe Johansen
parent
f3b7e3281a
commit
b98eb3daa9
@ -76,7 +76,7 @@ unit cgrv;
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const
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TOpCmp2AsmCond: Array[topcmp] of TAsmCond = (C_NONE,C_EQ,C_NONE,
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C_LT,C_GE,C_None,C_NE,C_NONE,C_LT,C_GE,C_NONE);
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C_LT,C_GE,C_None,C_NE,C_NONE,C_LTU,C_GEU,C_NONE);
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const
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TOpCG2AsmConstOp: Array[topcg] of TAsmOp = (A_NONE,
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@ -98,7 +98,6 @@ unit cgrv;
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procedure tcgrv.a_call_name(list : TAsmList;const s : string; weak: boolean);
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var
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tmpreg: TRegister;
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href: treference;
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l: TAsmLabel;
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begin
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@ -107,26 +106,20 @@ unit cgrv;
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else
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reference_reset_symbol(href,current_asmdata.WeakRefAsmSymbol(s,AT_FUNCTION),0,0,[]);
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tmpreg:=getintregister(list,OS_ADDR);
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current_asmdata.getjumplabel(l);
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a_label(list,l);
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href.refaddr:=addr_pcrel_hi20;
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list.concat(taicpu.op_reg_ref(A_AUIPC,tmpreg,href));
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list.concat(taicpu.op_reg_ref(A_AUIPC,NR_RETURN_ADDRESS_REG,href));
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reference_reset_symbol(href,l,0,0,[]);
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href.refaddr:=addr_pcrel_lo12;
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list.concat(taicpu.op_reg_reg_ref(A_JALR,NR_RETURN_ADDRESS_REG,tmpreg,href));
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list.concat(taicpu.op_reg_reg_ref(A_JALR,NR_RETURN_ADDRESS_REG,NR_RETURN_ADDRESS_REG,href));
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{if not(weak) then
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list.concat(taicpu.op_reg_sym(A_JAL,NR_RETURN_ADDRESS_REG,current_asmdata.RefAsmSymbol(s,AT_FUNCTION)))
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else
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list.concat(taicpu.op_reg_sym(A_JAL,NR_RETURN_ADDRESS_REG,current_asmdata.WeakRefAsmSymbol(s,AT_FUNCTION)));}
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{ not assigned while generating external wrappers }
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if assigned(current_procinfo) then
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include(current_procinfo.flags,pi_do_call);
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{ not assigned while generating external wrappers }
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if assigned(current_procinfo) then
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include(current_procinfo.flags,pi_do_call);
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end;
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@ -239,46 +232,41 @@ unit cgrv;
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procedure tcgrv.a_op_reg_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister);
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begin
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case op of
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OP_NOT:
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begin
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list.concat(taicpu.op_reg_reg_const(A_XORI,dst,src1,-1));
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maybeadjustresult(list,op,size,dst);
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end;
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OP_NEG:
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SUB,dst,NR_X0,src1));
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maybeadjustresult(list,op,size,dst);
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end;
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OP_MOVE:
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a_load_reg_reg(list,size,size,src1,dst);
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if op=OP_NOT then
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a_op_const_reg_reg(list,OP_XOR,size,-1,src1,dst)
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else if op=OP_NEG then
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a_op_reg_reg_reg(list,OP_SUB,size,src1,NR_X0,dst)
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else
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{$ifdef RISCV64}
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if (op=OP_SHL) and
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(size in [OS_32,OS_S32]) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SLLW,dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end
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else if (op=OP_SHR) and
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(size in [OS_32,OS_S32]) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SRLW,dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end
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else if (op=OP_SAR) and
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(size in [OS_32,OS_S32]) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SRAW,dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end
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case op of
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OP_MOVE:
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a_load_reg_reg(list,size,size,src1,dst);
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else
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{$ifdef RISCV64}
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if (op=OP_SHL) and
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(size in [OS_32,OS_S32]) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SLLW,dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end
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else if (op=OP_SHR) and
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(size in [OS_32,OS_S32]) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SRLW,dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end
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else if (op=OP_SAR) and
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(size in [OS_32,OS_S32]) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SRAW,dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end
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else
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{$endif RISCV64}
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begin
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list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end;
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end;
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begin
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list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end;
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end;
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end;
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@ -509,6 +497,8 @@ unit cgrv;
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end;
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list.concat(taicpu.op_reg_ref(op,reg,href));
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if fromsize<>tosize then
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a_load_reg_reg(list,fromsize,tosize,reg,reg);
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end;
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@ -96,7 +96,11 @@ implementation
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var
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ai: taicpu;
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begin
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if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
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if (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_S32) then
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list.Concat(taicpu.op_reg_reg_const(A_ADDIW,reg2,reg1,0))
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else if (tcgsize2unsigned[tosize]=OS_64) and (fromsize=OS_8) then
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list.Concat(taicpu.op_reg_reg_const(A_ANDI,reg2,reg1,$FF))
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else if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
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((tcgsize2size[fromsize] = tcgsize2size[tosize]) and (fromsize <> tosize)) or
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{ do we need to mask out the sign when loading from smaller signed to larger unsigned type? }
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((tcgsize2unsigned[fromsize]<>fromsize) and ((tcgsize2unsigned[tosize]=tosize)) and
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@ -142,8 +146,7 @@ implementation
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list.concat(taicpu.op_reg_reg_const(A_ADDI,register,NR_X0,a))
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else if is_lui_imm(a) then
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list.concat(taicpu.op_reg_const(A_LUI,register,(a shr 12) and $FFFFF))
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else if (qword(longint(a))=a) and
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(size in [OS_32,OS_S32]) then
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else if (int64(longint(a))=a) then
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begin
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if (a and $800)<>0 then
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list.concat(taicpu.op_reg_const(A_LUI,register,((a shr 12)+1) and $FFFFF))
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@ -227,6 +230,11 @@ implementation
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jump if not sum<x
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}
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tmpreg:=getintregister(list,OS_INT);
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if size in [OS_S32,OS_32] then
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begin
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a_load_reg_reg(list,size,OS_64,dst,tmpreg);
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dst:=tmpreg;
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end;
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list.Concat(taicpu.op_reg_reg_reg(A_SLTU,tmpreg,dst,src));
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ai:=taicpu.op_reg_reg_sym_ofs(A_Bxx,tmpreg,NR_X0,l,0);
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@ -287,6 +295,12 @@ implementation
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jump if not sum<x
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}
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tmpreg:=getintregister(list,OS_INT);
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if size in [OS_S32,OS_32] then
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begin
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a_load_reg_reg(list,size,OS_64,dst,tmpreg);
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dst:=tmpreg;
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end;
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tmpreg:=getintregister(list,OS_INT);
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list.Concat(taicpu.op_reg_reg_reg(A_SLTU,tmpreg,dst,src2));
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ai:=taicpu.op_reg_reg_sym_ofs(A_Bxx,tmpreg,NR_X0,l,0);
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@ -32,14 +32,14 @@ function get_frame:pointer;assembler;nostackframe;
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{$define FPC_SYSTEM_HAS_GET_CALLER_ADDR}
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function get_caller_addr(framebp:pointer;addr:pointer=nil):pointer;assembler;
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asm
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ld a0, -8*2(a0)
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ld a0, -8*1(a0)
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end;
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{$define FPC_SYSTEM_HAS_GET_CALLER_FRAME}
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function get_caller_frame(framebp:pointer;addr:pointer=nil):pointer;assembler;
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asm
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ld a0, -8*1(a0)
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ld a0, -8*2(a0)
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end;
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