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+ added shift support
This commit is contained in:
mazen
parent
00ee9f8063
commit
b9a1c74a71
546
compiler/sparc/ncpumat.pas
Normal file
546
compiler/sparc/ncpumat.pas
Normal file
@ -0,0 +1,546 @@
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{
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$Id$
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate PowerPC assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncpumat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat;
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type
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tSparcmoddivnode = class(tmoddivnode)
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procedure pass_2;override;
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end;
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tSparcshlshrnode = class(tshlshrnode)
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procedure pass_2;override;
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{ everything will be handled in pass_2 }
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function first_shlshr64bitint: tnode; override;
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end;
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tSparcunaryminusnode = class(tunaryminusnode)
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procedure pass_2;override;
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end;
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tSparcnotnode = class(tnotnode)
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procedure pass_2;override;
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end;
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implementation
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uses
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globtype,systems,
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cutils,verbose,globals,
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symconst,symdef,
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aasmbase,aasmcpu,aasmtai,
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defutil,
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cgbase,cgobj,pass_1,pass_2,
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ncon,
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cpubase,cpuinfo,cginfo,
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ncgutil,cga,cgcpu,cg64f32,rgobj;
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{*****************************************************************************
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TSparcMODDIVNODE
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*****************************************************************************}
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procedure tSparcmoddivnode.pass_2;
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const
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{ signed overflow }
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divops: array[boolean, boolean] of tasmop =
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((A_SDIV,A_UDIV),(A_SDIVcc,A_UDIVcc));
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var
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power,
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l1, l2 : longint;
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op : tasmop;
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numerator,
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divider,
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resultreg : tregister;
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saved : tmaybesave;
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begin
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secondpass(left);
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maybe_save(exprasmlist,right.registers32,left.location,saved);
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secondpass(right);
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maybe_restore(exprasmlist,left.location,saved);
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location_copy(location,left.location);
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{ put numerator in register }
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location_force_reg(exprasmlist,left.location,
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def_cgsize(left.resulttype.def),true);
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location_copy(location,left.location);
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numerator := location.register;
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resultreg := location.register;
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if (location.loc = LOC_CREGISTER) then
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begin
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location.loc := LOC_REGISTER;
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location.register := rg.getregisterint(exprasmlist);
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resultreg := location.register;
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end;
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if (nodetype = modn) then
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begin
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resultreg := cg.get_scratch_reg_int(exprasmlist);
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end;
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if (nodetype = divn) and
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(right.nodetype = ordconstn) and
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ispowerof2(tordconstnode(right).value,power) then
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begin
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{ From "The PowerPC Compiler Writer's Guide": }
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{ This code uses the fact that, in the PowerPC architecture, }
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{ the shift right algebraic instructions set the Carry bit if }
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{ the source register contains a negative number and one or }
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{ more 1-bits are shifted out. Otherwise, the carry bit is }
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{ cleared. The addze instruction corrects the quotient, if }
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{ necessary, when the dividend is negative. For example, if }
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{ n = -13, (0xFFFF_FFF3), and k = 2, after executing the srawi }
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{ instruction, q = -4 (0xFFFF_FFFC) and CA = 1. After executing }
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{ the addze instruction, q = -3, the correct quotient. }
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cg.a_op_const_reg_reg(exprasmlist,OP_SAR,OS_32,aword(power),
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numerator,resultreg);
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exprasmlist.concat(taicpu.op_reg_reg(A_ADD,resultreg,resultreg));
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end
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else
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begin
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{ load divider in a register if necessary }
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location_force_reg(exprasmlist,right.location,
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def_cgsize(right.resulttype.def),true);
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divider := right.location.register;
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{ needs overflow checking, (-maxlongint-1) div (-1) overflows! }
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{ And on Sparc, the only way to catch a div-by-0 is by checking }
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{ the overflow flag (JM) }
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op := divops[is_signed(right.resulttype.def),
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cs_check_overflow in aktlocalswitches];
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exprasmlist.concat(taicpu.op_reg_reg_reg(op,resultreg,numerator,
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divider));
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if (nodetype = modn) then
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begin
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_SMUL,resultreg,
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divider,resultreg));
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rg.ungetregister(exprasmlist,divider);
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUB,location.register,
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numerator,resultreg));
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cg.free_scratch_reg(exprasmlist,resultreg);
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resultreg := location.register;
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end
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else
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rg.ungetregister(exprasmlist,divider);
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end;
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{ free used registers }
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if numerator <> resultreg then
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rg.ungetregisterint(exprasmlist,numerator);
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{ set result location }
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location.loc:=LOC_REGISTER;
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location.register:=resultreg;
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cg.g_overflowcheck(exprasmlist,self);
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end;
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{*****************************************************************************
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TSparcSHLRSHRNODE
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*****************************************************************************}
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function TSparcShlShrNode.first_shlshr64bitint:TNode;
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begin
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result := nil;
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end;
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procedure tSparcshlshrnode.pass_2;
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var
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resultreg, hregister1,hregister2,
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hregisterhigh,hregisterlow : tregister;
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op : topcg;
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asmop1, asmop2: tasmop;
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shiftval: aword;
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saved : tmaybesave;
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begin
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secondpass(left);
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maybe_save(exprasmlist,right.registers32,left.location,saved);
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secondpass(right);
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maybe_restore(exprasmlist,left.location,saved);
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if is_64bitint(left.resulttype.def)
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then
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begin
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location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
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location_copy(location,left.location);
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hregisterhigh := location.registerhigh;
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hregisterlow := location.registerlow;
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if (location.loc = LOC_CREGISTER)
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then
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begin
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location.loc := LOC_REGISTER;
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location.registerhigh := rg.getregisterint(exprasmlist);
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location.registerlow := rg.getregisterint(exprasmlist);
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end;
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if (right.nodetype = ordconstn)
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then
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begin
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shiftval := tordconstnode(right).value;
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if tordconstnode(right).value > 31
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then
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begin
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if nodetype = shln
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then
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begin
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if (shiftval and 31) <> 0
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then
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cg.a_op_const_reg_reg(exprasmlist,OP_SHL,OS_32,shiftval and 31,hregisterlow,location.registerhigh);
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cg.a_load_const_reg(exprasmlist,OS_32,0,location.registerlow);
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end
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else
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begin
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if (shiftval and 31) <> 0
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then
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cg.a_op_const_reg_reg(exprasmlist,OP_SHR,OS_32,shiftval and 31,hregisterhigh,location.registerlow);
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cg.a_load_const_reg(exprasmlist,OS_32,0,location.registerhigh);
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end;
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end
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else
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begin
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if nodetype = shln
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then
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begin
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{exprasmlist.concat(taicpu.op_reg_reg_const_const_const(A_RLWINM,location.registerhigh,hregisterhigh,shiftval,0,31-shiftval));
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(A_RLWIMI,location.registerhigh,hregisterlow,shiftval,32-shiftval,31));
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(A_RLWINM,location.registerlow,hregisterlow,shiftval,0,31-shiftval));}
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end
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else
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begin
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{exprasmlist.concat(taicpu.op_reg_reg_const_const_const(A_RLWINM,location.registerlow,hregisterlow,32-shiftval,shiftval,31));
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(A_RLWIMI,location.registerlow,hregisterhigh,32-shiftval,0,shiftval-1));
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exprasmlist.concat(taicpu.op_reg_reg_const_const_const(A_RLWINM,location.registerhigh,hregisterhigh,32-shiftval,shiftval,31));}
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end;
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end;
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end
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else
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{ no constant shiftcount }
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begin
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location_force_reg(exprasmlist,right.location,OS_S32,true);
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hregister1 := right.location.register;
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if nodetype = shln
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then
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begin
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asmop1 := A_SLL;
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asmop2 := A_SRL;
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end
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else
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begin
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asmop1 := A_SRL;
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asmop2 := A_SLL;
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resultreg := location.registerhigh;
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location.registerhigh := location.registerlow;
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location.registerlow := resultreg;
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end;
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rg.getexplicitregisterint(exprasmlist,R_G0);
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{ exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBFIC,R_0,hregister1,32));
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exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,location.registerhigh,hregisterhigh,hregister1));
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exprasmlist.concat(taicpu.op_reg_reg_reg(asmop2,R_0,hregisterlow,R_0));
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_OR,location.registerhigh,location.registerhigh,R_0));
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exprasmlist.concat(taicpu.op_reg_reg_const(A_SUBI,R_0,hregister1,32));
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exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,R_0,hregisterlow,R_0));
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exprasmlist.concat(taicpu.op_reg_reg_reg(A_OR,location.registerhigh,location.registerhigh,R_0));
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exprasmlist.concat(taicpu.op_reg_reg_reg(asmop1,location.registerlow,hregisterlow,hregister1));}
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rg.ungetregister(exprasmlist,R_G0);
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if right.location.loc in [LOC_CREFERENCE,LOC_REFERENCE]
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then
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cg.free_scratch_reg(exprasmlist,hregister1)
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else
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rg.ungetregister(exprasmlist,hregister1);
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end
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end
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else
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begin
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{ load left operators in a register }
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location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
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location_copy(location,left.location);
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resultreg := location.register;
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hregister1 := location.register;
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if (location.loc = LOC_CREGISTER)
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then
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begin
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location.loc := LOC_REGISTER;
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resultreg := rg.getregisterint(exprasmlist);
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location.register := resultreg;
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end;
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{ determine operator }
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if nodetype=shln
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then
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op:=OP_SHL
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else
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op:=OP_SHR;
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn)
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then
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cg.a_op_const_reg_reg(exprasmlist,op,OS_32,tordconstnode(right).value and 31,hregister1,resultreg)
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else
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begin
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{ load shift count in a register if necessary }
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location_force_reg(exprasmlist,right.location,def_cgsize(right.resulttype.def),true);
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hregister2 := right.location.register;
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cg.a_op_reg_reg_reg(exprasmlist,op,OS_32,hregister2,hregister1,resultreg);
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rg.ungetregister(exprasmlist,hregister2);
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end;
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end;
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end;
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{*****************************************************************************
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TSparcUNARYMINUSNODE
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*****************************************************************************}
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procedure tSparcunaryminusnode.pass_2;
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var
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src1, src2, tmp: tregister;
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op: tasmop;
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begin
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secondpass(left);
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if is_64bitint(left.resulttype.def) then
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begin
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location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
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location_copy(location,left.location);
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if (location.loc = LOC_CREGISTER) then
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begin
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location.registerlow := rg.getregisterint(exprasmlist);
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location.registerhigh := rg.getregisterint(exprasmlist);
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location.loc := LOC_CREGISTER;
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end;
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exprasmlist.concat(taicpu.op_reg_const_reg(A_SUB,location.registerlow,0,left.location.registerlow));
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if not(cs_check_overflow in aktlocalswitches) then
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exprasmlist.concat(taicpu.op_reg_reg(A_SUB,location.registerhigh,left.location.registerhigh))
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else
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exprasmlist.concat(taicpu.op_reg_reg(A_SUB,location.registerhigh,left.location.registerhigh));
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end
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else
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begin
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location_copy(location,left.location);
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location.loc:=LOC_REGISTER;
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case left.location.loc of
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LOC_FPUREGISTER, LOC_REGISTER:
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begin
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src1 := left.location.register;
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location.register := src1;
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end;
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LOC_CFPUREGISTER, LOC_CREGISTER:
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begin
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src1 := left.location.register;
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if left.location.loc = LOC_CREGISTER then
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location.register := rg.getregisterint(exprasmlist)
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else
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location.register := rg.getregisterfpu(exprasmlist);
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end;
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LOC_REFERENCE,LOC_CREFERENCE:
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begin
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if (left.resulttype.def.deftype=floatdef) then
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begin
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src1 := rg.getregisterfpu(exprasmlist);
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location.register := src1;
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cg.a_loadfpu_ref_reg(exprasmlist,
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def_cgsize(left.resulttype.def),
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left.location.reference,src1);
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end
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else
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begin
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src1 := rg.getregisterint(exprasmlist);
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location.register:= src1;
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cg.a_load_ref_reg(exprasmlist,OS_32,
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left.location.reference,src1);
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end;
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reference_release(exprasmlist,left.location.reference);
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end;
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end;
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{ choose appropriate operand }
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if left.resulttype.def.deftype <> floatdef then
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begin
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if not(cs_check_overflow in aktlocalswitches) then
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op := A_NEG
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else
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op := A_NEG;
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location.loc := LOC_REGISTER;
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end
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else
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begin
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op := A_NEG;
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location.loc := LOC_FPUREGISTER;
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end;
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{ emit operation }
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exprasmlist.concat(taicpu.op_reg_reg(op,location.register,src1));
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end;
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{ Here was a problem... }
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{ Operand to be negated always }
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{ seems to be converted to signed }
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{ 32-bit before doing neg!! }
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{ So this is useless... }
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{ that's not true: -2^31 gives an overflow error if it is negated (FK) }
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cg.g_overflowcheck(exprasmlist,self);
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end;
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{*****************************************************************************
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TSparcNOTNODE
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*****************************************************************************}
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procedure tSparcnotnode.pass_2;
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var
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hl : tasmlabel;
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regl, regh: tregister;
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begin
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if is_boolean(resulttype.def) then
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begin
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{ the second pass could change the location of left }
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{ if it is a register variable, so we've to do }
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{ this before the case statement }
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if left.location.loc in [LOC_REFERENCE,LOC_CREFERENCE,
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LOC_FLAGS,LOC_REGISTER,LOC_CREGISTER] then
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secondpass(left);
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case left.location.loc of
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LOC_JUMP :
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begin
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hl:=truelabel;
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truelabel:=falselabel;
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falselabel:=hl;
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secondpass(left);
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maketojumpbool(exprasmlist,left,lr_load_regvars);
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hl:=truelabel;
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truelabel:=falselabel;
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falselabel:=hl;
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end;
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LOC_FLAGS :
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begin
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location_copy(location,left.location);
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//inverse_flags(location.resflags);
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end;
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LOC_REGISTER, LOC_CREGISTER, LOC_REFERENCE, LOC_CREFERENCE :
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begin
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location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),true);
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exprasmlist.concat(taicpu.op_reg_const(A_SUBcc,left.location.register,0));
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location_release(exprasmlist,left.location);
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location_reset(location,LOC_FLAGS,OS_NO);
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//location.resflags.cr:=r_NONE;
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//location.resflags.flag:=F_NONE;
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end;
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end;
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||||
end
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else if is_64bitint(left.resulttype.def) then
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begin
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||||
secondpass(left);
|
||||
location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),false);
|
||||
location_copy(location,left.location);
|
||||
{ perform the NOT operation }
|
||||
exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.registerhigh,
|
||||
location.registerhigh));
|
||||
exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.registerlow,
|
||||
location.registerlow));
|
||||
end
|
||||
else
|
||||
begin
|
||||
secondpass(left);
|
||||
location_force_reg(exprasmlist,left.location,def_cgsize(left.resulttype.def),false);
|
||||
location_copy(location,left.location);
|
||||
if location.loc=LOC_CREGISTER then
|
||||
location.register := rg.getregisterint(exprasmlist);
|
||||
{ perform the NOT operation }
|
||||
exprasmlist.concat(taicpu.op_reg_reg(A_NOT,location.register,
|
||||
left.location.register));
|
||||
end;
|
||||
end;
|
||||
|
||||
begin
|
||||
cmoddivnode:=tSparcmoddivnode;
|
||||
cshlshrnode:=tSparcshlshrnode;
|
||||
cunaryminusnode:=tSparcunaryminusnode;
|
||||
cnotnode:=tSparcnotnode;
|
||||
end.
|
||||
{
|
||||
$Log$
|
||||
Revision 1.1 2002-12-21 23:22:59 mazen
|
||||
+ added shift support
|
||||
|
||||
Revision 1.20 2002/11/25 17:43:28 peter
|
||||
* splitted defbase in defutil,symutil,defcmp
|
||||
* merged isconvertable and is_equal into compare_defs(_ext)
|
||||
* made operator search faster by walking the list only once
|
||||
|
||||
Revision 1.19 2002/09/10 21:21:29 jonas
|
||||
* fixed unary minus of 64bit values
|
||||
|
||||
Revision 1.18 2002/09/07 15:25:14 peter
|
||||
* old logs removed and tabs fixed
|
||||
|
||||
Revision 1.17 2002/08/15 15:15:55 carl
|
||||
* jmpbuf size allocation for exceptions is now cpu specific (as it should)
|
||||
* more generic nodes for maths
|
||||
* several fixes for better m68k support
|
||||
|
||||
Revision 1.16 2002/08/10 17:15:31 jonas
|
||||
* various fixes and optimizations
|
||||
|
||||
Revision 1.15 2002/07/26 10:48:34 jonas
|
||||
* fixed bug in shl/shr code
|
||||
|
||||
Revision 1.14 2002/07/20 11:58:05 florian
|
||||
* types.pas renamed to defbase.pas because D6 contains a types
|
||||
unit so this would conflicts if D6 programms are compiled
|
||||
+ Willamette/SSE2 instructions to assembler added
|
||||
|
||||
Revision 1.13 2002/07/11 07:41:27 jonas
|
||||
* fixed tSparcmoddivnode
|
||||
* fixed 64bit parts of tSparcshlshrnode
|
||||
|
||||
Revision 1.12 2002/07/09 19:45:01 jonas
|
||||
* unarynminus and shlshr node fixed for 32bit and smaller ordinals
|
||||
* small fixes in the assembler writer
|
||||
* changed scratch registers, because they were used by the linker (r11
|
||||
and r12) and by the abi under linux (r31)
|
||||
|
||||
Revision 1.11 2002/07/07 09:44:32 florian
|
||||
* powerpc target fixed, very simple units can be compiled
|
||||
|
||||
Revision 1.10 2002/05/20 13:30:42 carl
|
||||
* bugfix of hdisponen (base must be set, not index)
|
||||
* more portability fixes
|
||||
|
||||
Revision 1.9 2002/05/18 13:34:26 peter
|
||||
* readded missing revisions
|
||||
|
||||
Revision 1.8 2002/05/16 19:46:53 carl
|
||||
+ defines.inc -> fpcdefs.inc to avoid conflicts if compiling by hand
|
||||
+ try to fix temp allocation (still in ifdef)
|
||||
+ generic constructor calls
|
||||
+ start of tassembler / tmodulebase class cleanup
|
||||
|
||||
Revision 1.5 2002/05/13 19:52:46 peter
|
||||
* a ppcSparc can be build again
|
||||
|
||||
Revision 1.4 2002/04/21 15:48:39 carl
|
||||
* some small updates according to i386 version
|
||||
|
||||
Revision 1.3 2002/04/06 18:13:02 jonas
|
||||
* several powerpc-related additions and fixes
|
||||
|
||||
Revision 1.2 2002/01/03 14:57:52 jonas
|
||||
* completed (not compilale yet though)
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user