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* Risc-V: return with mret from interrupt handlers, resolves #39737

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This commit is contained in:
florian 2022-05-27 23:31:28 +02:00
parent b810afa193
commit ca29df1aa9
2 changed files with 12 additions and 2 deletions
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7
compiler/riscv32/cgcpu.pas
View File

@ -323,7 +323,12 @@ unit cgcpu;
end;
end;
list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG));
if po_interrupt in current_procinfo.procdef.procoptions then
begin
list.concat(Taicpu.Op_none(A_MRET));
end
else
list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG));
end;

7
compiler/riscv64/cgcpu.pas
View File

@ -513,7 +513,12 @@ implementation
end;
end;
list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG));
if po_interrupt in current_procinfo.procdef.procoptions then
begin
list.concat(Taicpu.Op_none(A_MRET));
end
else
list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG));
end;