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* fixes several register allocation related mips issues
* fixes range check error in mips code git-svn-id: trunk@20266 -
This commit is contained in:
florian
parent
723482c814
commit
de4a96f96d
@ -517,10 +517,10 @@ begin
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first_int_imreg, []);
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first_int_imreg, []);
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rg[R_FPUREGISTER] := trgcpu.Create(R_FPUREGISTER, R_SUBFS{R_SUBFD},
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rg[R_FPUREGISTER] := trgcpu.Create(R_FPUREGISTER, R_SUBFS{R_SUBFD},
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[RS_F0, RS_F2, RS_F4, RS_F6,
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[RS_F0,RS_F1,RS_F2,RS_F3,RS_F4,RS_F5,RS_F6,RS_F7,
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RS_F8, RS_F10, RS_F12, RS_F14,
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RS_F8,RS_F9,RS_F10,RS_F11,RS_F12,RS_F13,RS_F14,RS_F15,
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RS_F16, RS_F18, RS_F20, RS_F22,
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RS_F16,RS_F17,RS_F18,RS_F19,RS_F20,RS_F21,RS_F22,RS_F23,
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RS_F24, RS_F26, RS_F28, RS_F30],
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RS_F24,RS_F25,RS_F26,RS_F27,RS_F28,RS_F29,RS_F30,RS_F31],
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first_fpu_imreg, []);
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first_fpu_imreg, []);
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{ needs at least one element for rgobj not to crash }
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{ needs at least one element for rgobj not to crash }
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@ -542,7 +542,7 @@ end;
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function TCgMPSel.getfpuregister(list: tasmlist; size: Tcgsize): Tregister;
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function TCgMPSel.getfpuregister(list: tasmlist; size: Tcgsize): Tregister;
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begin
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begin
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if size = OS_F64 then
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if size = OS_F64 then
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Result := rg[R_FPUREGISTER].getregister(list, R_SUBFD)
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Result := rg[R_FPUREGISTER].getregister(list, R_SUBFS)
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else
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else
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Result := rg[R_FPUREGISTER].getregister(list, R_SUBFS);
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Result := rg[R_FPUREGISTER].getregister(list, R_SUBFS);
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end;
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end;
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@ -696,7 +696,7 @@ begin
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list.concat(taicpu.op_reg_reg(A_MOVE, reg, NR_R0))
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list.concat(taicpu.op_reg_reg(A_MOVE, reg, NR_R0))
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{ LUI allows to set the upper 16 bits, so we'll take full advantage of it }
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{ LUI allows to set the upper 16 bits, so we'll take full advantage of it }
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else if (a and aint($ffff)) = 0 then
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else if (a and aint($ffff)) = 0 then
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list.concat(taicpu.op_reg_const(A_LUI, reg, a shr 16))
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list.concat(taicpu.op_reg_const(A_LUI, reg, aint(a) shr 16))
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else if (a >= simm16lo) and (a <= simm16hi) then
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else if (a >= simm16lo) and (a <= simm16hi) then
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list.concat(taicpu.op_reg_reg_const(A_ADDIU, reg, NR_R0, a))
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list.concat(taicpu.op_reg_reg_const(A_ADDIU, reg, NR_R0, a))
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else if (a>=0) and (a <= 65535) then
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else if (a>=0) and (a <= 65535) then
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@ -67,7 +67,7 @@ unit cpubase;
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{$i rmipssup.inc}
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{$i rmipssup.inc}
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{ No Subregisters }
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{ No Subregisters }
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R_SUBWHOLE = R_SUBNONE;
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R_SUBWHOLE = R_SUBD;
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{ Available Registers }
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{ Available Registers }
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{$i rmipscon.inc}
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{$i rmipscon.inc}
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@ -4,80 +4,80 @@
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; layout
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; layout
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; <name>,<value>,<stdname>,<gasname>,<stabidx>
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; <name>,<value>,<stdname>,<gasname>,<stabidx>
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;
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;
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NO,$00,$00,INVALID,INVALID,-1,-1
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NO,$00,$00,$00,INVALID,INVALID,-1,-1
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R0,$01,$00,zero,$0,0,0
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R0,$01,$04,$00,zero,$0,0,0
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R1,$01,$01,at,$1,1,1
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R1,$01,$04,$01,at,$1,1,1
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R2,$01,$02,v0,$2,2,2
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R2,$01,$04,$02,v0,$2,2,2
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R3,$01,$03,v1,$3,3,3
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R3,$01,$04,$03,v1,$3,3,3
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R4,$01,$04,a0,$4,4,4
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R4,$01,$04,$04,a0,$4,4,4
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R5,$01,$05,a1,$5,5,5
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R5,$01,$04,$05,a1,$5,5,5
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R6,$01,$06,a2,$6,6,6
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R6,$01,$04,$06,a2,$6,6,6
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R7,$01,$07,a3,$7,7,7
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R7,$01,$04,$07,a3,$7,7,7
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R8,$01,$08,t0,$8,8,8
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R8,$01,$04,$08,t0,$8,8,8
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R9,$01,$09,t1,$9,9,9
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R9,$01,$04,$09,t1,$9,9,9
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R10,$01,$0a,t2,$10,10,10
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R10,$01,$04,$0A,t2,$10,10,10
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R11,$01,$0b,t3,$11,11,11
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R11,$01,$04,$0B,t3,$11,11,11
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R12,$01,$0c,t4,$12,12,12
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R12,$01,$04,$0C,t4,$12,12,12
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R13,$01,$0d,t5,$13,13,13
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R13,$01,$04,$0D,t5,$13,13,13
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R14,$01,$0e,t6,$14,14,14
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R14,$01,$04,$0E,t6,$14,14,14
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R15,$01,$0f,t7,$15,15,15
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R15,$01,$04,$0F,t7,$15,15,15
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R16,$01,$10,s0,$16,16,16
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R16,$01,$04,$10,s0,$16,16,16
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R17,$01,$11,s1,$17,17,17
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R17,$01,$04,$11,s1,$17,17,17
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R18,$01,$12,s2,$18,18,18
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R18,$01,$04,$12,s2,$18,18,18
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R19,$01,$13,s3,$19,19,19
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R19,$01,$04,$13,s3,$19,19,19
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R20,$01,$14,s4,$20,20,20
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R20,$01,$04,$14,s4,$20,20,20
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R21,$01,$15,s5,$21,21,21
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R21,$01,$04,$15,s5,$21,21,21
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R22,$01,$16,s6,$22,22,22
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R22,$01,$04,$16,s6,$22,22,22
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R23,$01,$17,s7,$23,23,23
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R23,$01,$04,$17,s7,$23,23,23
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R24,$01,$18,t8,$24,24,24
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R24,$01,$04,$18,t8,$24,24,24
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R25,$01,$19,t9,$25,25,25
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R25,$01,$04,$19,t9,$25,25,25
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R26,$01,$1a,k0,$26,26,26
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R26,$01,$04,$1A,k0,$26,26,26
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R27,$01,$1b,k1,$27,27,27
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R27,$01,$04,$1B,k1,$27,27,27
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R28,$01,$1c,gp,$28,28,28
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R28,$01,$04,$1C,gp,$28,28,28
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R29,$01,$1d,sp,$29,29,29
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R29,$01,$04,$1D,sp,$29,29,29
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R30,$01,$1e,fp,$30,30,30
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R30,$01,$04,$1E,fp,$30,30,30
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R31,$01,$1f,$a,$31,31,31
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R31,$01,$04,$1F,$a,$31,31,31
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F0,$02,$06,F0,f0,32,32
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F0,$02,$06,$00,F0,$0,32,32
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F1,$02,$06,F1,f1,33,33
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F1,$02,$06,$01,F1,$1,33,33
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F2,$02,$06,F2,f2,34,34
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F2,$02,$06,$02,F2,$2,34,34
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F3,$02,$06,F3,f3,35,35
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F3,$02,$06,$03,F3,$3,35,35
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F4,$02,$06,F4,f4,36,36
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F4,$02,$06,$04,F4,$4,36,36
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F5,$02,$06,F5,f5,37,37
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F5,$02,$06,$05,F5,$5,37,37
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F6,$02,$06,F6,f6,38,38
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F6,$02,$06,$06,F6,$6,38,38
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F7,$02,$06,F7,f7,39,39
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F7,$02,$06,$07,F7,$7,39,39
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F8,$02,$06,F8,f8,40,40
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F8,$02,$06,$08,F8,$8,40,40
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F9,$02,$06,F9,f9,41,41
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F9,$02,$06,$09,F9,$9,41,41
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F10,$02,$06,F10,f10,42,42
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F10,$02,$06,$0A,F10,$10,42,42
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F11,$02,$06,F11,f11,43,43
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F11,$02,$06,$0B,F11,$11,43,43
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F12,$02,$06,F12,f12,44,44
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F12,$02,$06,$0C,F12,$12,44,44
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F13,$02,$06,F13,f13,45,45
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F13,$02,$06,$0D,F13,$13,45,45
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F14,$02,$06,F14,f14,46,46
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F14,$02,$06,$0E,F14,$14,46,46
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F15,$02,$06,F15,f15,47,47
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F15,$02,$06,$0F,F15,$15,47,47
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F16,$02,$06,F16,f16,48,48
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F16,$02,$06,$10,F16,$16,48,48
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F17,$02,$06,F17,f17,49,49
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F17,$02,$06,$11,F17,$17,49,49
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F18,$02,$06,F18,f18,50,50
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F18,$02,$06,$12,F18,$18,50,50
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F19,$02,$06,F19,f19,51,51
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F19,$02,$06,$13,F19,$19,51,51
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F20,$02,$06,F20,f20,52,52
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F20,$02,$06,$14,F20,$20,52,52
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F21,$02,$06,F21,f21,53,53
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F21,$02,$06,$15,F21,$21,53,53
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F22,$02,$06,F22,f22,54,54
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F22,$02,$06,$16,F22,$22,54,54
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F23,$02,$06,F23,f23,55,55
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F23,$02,$06,$17,F23,$23,55,55
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F24,$02,$06,F24,f24,56,56
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F24,$02,$06,$18,F24,$24,56,56
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F25,$02,$06,F25,f25,57,57
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F25,$02,$06,$19,F25,$25,57,57
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F26,$02,$06,F26,f26,58,58
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F26,$02,$06,$1A,F26,$26,58,58
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F27,$02,$06,F27,f27,59,59
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F27,$02,$06,$1B,F27,$27,59,59
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F28,$02,$06,F28,f28,60,60
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F28,$02,$06,$1C,F28,$28,60,60
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F29,$02,$06,F29,f29,61,61
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F29,$02,$06,$1D,F29,$29,61,61
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F30,$02,$06,F30,f30,62,62
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F30,$02,$06,$1E,F30,$30,62,62
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F31,$02,$06,F31,f31,63,63
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F31,$02,$06,$1F,F31,$31,63,63
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PC,$05,$00,PC,pc,-1,-1
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PC,$05,$00,$00,PC,pc,-1,-1
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HI,$05,$01,HI,hi,68,68
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HI,$05,$00,$01,HI,hi,68,68
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LO,$05,$02,LO,lo,69,69
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LO,$05,$00,$02,LO,lo,69,69
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CR,$05,$03,CR,cr,70,70
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CR,$05,$00,$03,CR,cr,70,70
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FCR0,$05,$04,FCR0,fcr0,71,71
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FCR0,$05,$00,$04,FCR0,fcr0,71,71
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FCR25,$05,$05,FCR25,fcr25,72,72
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FCR25,$05,$00,$05,FCR25,fcr25,72,72
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FCR26,$05,$06,FCR26,fcr26,73,73
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FCR26,$05,$00,$06,FCR26,fcr26,73,73
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FCR28,$05,$07,FCR28,fcr28,74,74
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FCR28,$05,$00,$07,FCR28,fcr28,74,74
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FCSR,$05,$08,FCSR,fcsr,75,75
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FCSR,$05,$00,$08,FCSR,fcsr,75,75
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@ -117,7 +117,8 @@ implementation
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helpins:=spilling_create_load(tmpref,tempreg);
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helpins:=spilling_create_load(tmpref,tempreg);
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helplist.concat(helpins);
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helplist.concat(helpins);
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list.insertlistafter(pos,helplist)
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list.insertlistafter(pos,helplist);
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helplist.free;
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end
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end
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else
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else
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inherited do_spill_read(list,pos,spilltemp,tempreg);
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inherited do_spill_read(list,pos,spilltemp,tempreg);
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@ -126,7 +127,6 @@ implementation
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procedure trgcpu.do_spill_written(list:tasmlist;pos:tai;const spilltemp:treference;tempreg:tregister);
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procedure trgcpu.do_spill_written(list:tasmlist;pos:tai;const spilltemp:treference;tempreg:tregister);
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var
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var
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helpins : tai;
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tmpref : treference;
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tmpref : treference;
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helplist : tasmlist;
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helplist : tasmlist;
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hreg : tregister;
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hreg : tregister;
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@ -151,12 +151,12 @@ implementation
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reference_reset_base(tmpref,hreg,0,sizeof(aint));
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reference_reset_base(tmpref,hreg,0,sizeof(aint));
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helpins:=spilling_create_store(tempreg,tmpref);
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helplist.concat(spilling_create_store(tempreg,tmpref));
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helplist.concat(helpins);
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if getregtype(tempreg)=R_INTREGISTER then
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if getregtype(tempreg)=R_INTREGISTER then
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ungetregisterinline(helplist,hreg);
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ungetregisterinline(helplist,hreg);
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list.insertlistafter(pos,helplist)
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list.insertlistafter(pos,helplist);
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helplist.free;
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end
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end
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else
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else
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inherited do_spill_written(list,pos,spilltemp,tempreg);
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inherited do_spill_written(list,pos,spilltemp,tempreg);
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@ -1,69 +1,69 @@
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{ don't edit, this file is generated from mipsreg.dat }
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{ don't edit, this file is generated from mipsreg.dat }
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NR_NO = tregister($00000000);
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NR_NO = tregister($00000000);
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NR_R0 = tregister($01000000);
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NR_R0 = tregister($01040000);
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NR_R1 = tregister($01000001);
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NR_R1 = tregister($01040001);
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NR_R2 = tregister($01000002);
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NR_R2 = tregister($01040002);
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NR_R3 = tregister($01000003);
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NR_R3 = tregister($01040003);
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NR_R4 = tregister($01000004);
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NR_R4 = tregister($01040004);
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NR_R5 = tregister($01000005);
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NR_R5 = tregister($01040005);
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NR_R6 = tregister($01000006);
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NR_R6 = tregister($01040006);
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NR_R7 = tregister($01000007);
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NR_R7 = tregister($01040007);
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NR_R8 = tregister($01000008);
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NR_R8 = tregister($01040008);
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NR_R9 = tregister($01000009);
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NR_R9 = tregister($01040009);
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NR_R10 = tregister($0100000a);
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NR_R10 = tregister($0104000A);
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NR_R11 = tregister($0100000b);
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NR_R11 = tregister($0104000B);
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NR_R12 = tregister($0100000c);
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NR_R12 = tregister($0104000C);
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NR_R13 = tregister($0100000d);
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NR_R13 = tregister($0104000D);
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NR_R14 = tregister($0100000e);
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NR_R14 = tregister($0104000E);
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NR_R15 = tregister($0100000f);
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NR_R15 = tregister($0104000F);
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NR_R16 = tregister($01000010);
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NR_R16 = tregister($01040010);
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NR_R17 = tregister($01000011);
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NR_R17 = tregister($01040011);
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NR_R18 = tregister($01000012);
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NR_R18 = tregister($01040012);
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NR_R19 = tregister($01000013);
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NR_R19 = tregister($01040013);
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NR_R20 = tregister($01000014);
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NR_R20 = tregister($01040014);
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NR_R21 = tregister($01000015);
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NR_R21 = tregister($01040015);
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NR_R22 = tregister($01000016);
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NR_R22 = tregister($01040016);
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NR_R23 = tregister($01000017);
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NR_R23 = tregister($01040017);
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NR_R24 = tregister($01000018);
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NR_R24 = tregister($01040018);
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NR_R25 = tregister($01000019);
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NR_R25 = tregister($01040019);
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NR_R26 = tregister($0100001a);
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NR_R26 = tregister($0104001A);
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NR_R27 = tregister($0100001b);
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NR_R27 = tregister($0104001B);
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NR_R28 = tregister($0100001c);
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NR_R28 = tregister($0104001C);
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NR_R29 = tregister($0100001d);
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NR_R29 = tregister($0104001D);
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NR_R30 = tregister($0100001e);
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NR_R30 = tregister($0104001E);
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NR_R31 = tregister($0100001f);
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NR_R31 = tregister($0104001F);
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NR_F0 = tregister($02000006);
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NR_F0 = tregister($02060000);
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NR_F1 = tregister($02000006);
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NR_F1 = tregister($02060001);
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NR_F2 = tregister($02000006);
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NR_F2 = tregister($02060002);
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NR_F3 = tregister($02000006);
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NR_F3 = tregister($02060003);
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NR_F4 = tregister($02000006);
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NR_F4 = tregister($02060004);
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NR_F5 = tregister($02000006);
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NR_F5 = tregister($02060005);
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NR_F6 = tregister($02000006);
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NR_F6 = tregister($02060006);
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NR_F7 = tregister($02000006);
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NR_F7 = tregister($02060007);
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NR_F8 = tregister($02000006);
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NR_F8 = tregister($02060008);
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NR_F9 = tregister($02000006);
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NR_F9 = tregister($02060009);
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NR_F10 = tregister($02000006);
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NR_F10 = tregister($0206000A);
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NR_F11 = tregister($02000006);
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NR_F11 = tregister($0206000B);
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NR_F12 = tregister($02000006);
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NR_F12 = tregister($0206000C);
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NR_F13 = tregister($02000006);
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NR_F13 = tregister($0206000D);
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NR_F14 = tregister($02000006);
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NR_F14 = tregister($0206000E);
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NR_F15 = tregister($02000006);
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NR_F15 = tregister($0206000F);
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NR_F16 = tregister($02000006);
|
NR_F16 = tregister($02060010);
|
||||||
NR_F17 = tregister($02000006);
|
NR_F17 = tregister($02060011);
|
||||||
NR_F18 = tregister($02000006);
|
NR_F18 = tregister($02060012);
|
||||||
NR_F19 = tregister($02000006);
|
NR_F19 = tregister($02060013);
|
||||||
NR_F20 = tregister($02000006);
|
NR_F20 = tregister($02060014);
|
||||||
NR_F21 = tregister($02000006);
|
NR_F21 = tregister($02060015);
|
||||||
NR_F22 = tregister($02000006);
|
NR_F22 = tregister($02060016);
|
||||||
NR_F23 = tregister($02000006);
|
NR_F23 = tregister($02060017);
|
||||||
NR_F24 = tregister($02000006);
|
NR_F24 = tregister($02060018);
|
||||||
NR_F25 = tregister($02000006);
|
NR_F25 = tregister($02060019);
|
||||||
NR_F26 = tregister($02000006);
|
NR_F26 = tregister($0206001A);
|
||||||
NR_F27 = tregister($02000006);
|
NR_F27 = tregister($0206001B);
|
||||||
NR_F28 = tregister($02000006);
|
NR_F28 = tregister($0206001C);
|
||||||
NR_F29 = tregister($02000006);
|
NR_F29 = tregister($0206001D);
|
||||||
NR_F30 = tregister($02000006);
|
NR_F30 = tregister($0206001E);
|
||||||
NR_F31 = tregister($02000006);
|
NR_F31 = tregister($0206001F);
|
||||||
NR_PC = tregister($05000000);
|
NR_PC = tregister($05000000);
|
||||||
NR_HI = tregister($05000001);
|
NR_HI = tregister($05000001);
|
||||||
NR_LO = tregister($05000002);
|
NR_LO = tregister($05000002);
|
||||||
|
|||||||
@ -32,38 +32,38 @@
|
|||||||
'$29',
|
'$29',
|
||||||
'$30',
|
'$30',
|
||||||
'$31',
|
'$31',
|
||||||
'f0',
|
'$0',
|
||||||
'f1',
|
'$1',
|
||||||
'f2',
|
'$2',
|
||||||
'f3',
|
'$3',
|
||||||
'f4',
|
'$4',
|
||||||
'f5',
|
'$5',
|
||||||
'f6',
|
'$6',
|
||||||
'f7',
|
'$7',
|
||||||
'f8',
|
'$8',
|
||||||
'f9',
|
'$9',
|
||||||
'f10',
|
'$10',
|
||||||
'f11',
|
'$11',
|
||||||
'f12',
|
'$12',
|
||||||
'f13',
|
'$13',
|
||||||
'f14',
|
'$14',
|
||||||
'f15',
|
'$15',
|
||||||
'f16',
|
'$16',
|
||||||
'f17',
|
'$17',
|
||||||
'f18',
|
'$18',
|
||||||
'f19',
|
'$19',
|
||||||
'f20',
|
'$20',
|
||||||
'f21',
|
'$21',
|
||||||
'f22',
|
'$22',
|
||||||
'f23',
|
'$23',
|
||||||
'f24',
|
'$24',
|
||||||
'f25',
|
'$25',
|
||||||
'f26',
|
'$26',
|
||||||
'f27',
|
'$27',
|
||||||
'f28',
|
'$28',
|
||||||
'f29',
|
'$29',
|
||||||
'f30',
|
'$30',
|
||||||
'f31',
|
'$31',
|
||||||
'pc',
|
'pc',
|
||||||
'hi',
|
'hi',
|
||||||
'lo',
|
'lo',
|
||||||
|
|||||||
@ -1,70 +1,70 @@
|
|||||||
{ don't edit, this file is generated from mipsreg.dat }
|
{ don't edit, this file is generated from mipsreg.dat }
|
||||||
1,
|
1,
|
||||||
2,
|
|
||||||
11,
|
|
||||||
12,
|
|
||||||
13,
|
|
||||||
14,
|
|
||||||
15,
|
|
||||||
16,
|
|
||||||
17,
|
|
||||||
18,
|
|
||||||
19,
|
|
||||||
20,
|
|
||||||
3,
|
|
||||||
21,
|
|
||||||
22,
|
|
||||||
23,
|
|
||||||
24,
|
|
||||||
25,
|
|
||||||
26,
|
|
||||||
27,
|
|
||||||
28,
|
|
||||||
29,
|
|
||||||
30,
|
|
||||||
4,
|
|
||||||
31,
|
|
||||||
32,
|
|
||||||
5,
|
|
||||||
6,
|
|
||||||
7,
|
|
||||||
8,
|
|
||||||
9,
|
|
||||||
10,
|
|
||||||
0,
|
|
||||||
68,
|
|
||||||
33,
|
33,
|
||||||
|
2,
|
||||||
34,
|
34,
|
||||||
|
11,
|
||||||
43,
|
43,
|
||||||
|
12,
|
||||||
44,
|
44,
|
||||||
|
13,
|
||||||
45,
|
45,
|
||||||
|
14,
|
||||||
46,
|
46,
|
||||||
|
15,
|
||||||
47,
|
47,
|
||||||
|
16,
|
||||||
48,
|
48,
|
||||||
|
17,
|
||||||
49,
|
49,
|
||||||
|
18,
|
||||||
50,
|
50,
|
||||||
|
19,
|
||||||
51,
|
51,
|
||||||
|
20,
|
||||||
52,
|
52,
|
||||||
|
3,
|
||||||
35,
|
35,
|
||||||
|
21,
|
||||||
53,
|
53,
|
||||||
|
22,
|
||||||
54,
|
54,
|
||||||
|
23,
|
||||||
55,
|
55,
|
||||||
|
24,
|
||||||
56,
|
56,
|
||||||
|
25,
|
||||||
57,
|
57,
|
||||||
|
26,
|
||||||
58,
|
58,
|
||||||
|
27,
|
||||||
59,
|
59,
|
||||||
|
28,
|
||||||
60,
|
60,
|
||||||
|
29,
|
||||||
61,
|
61,
|
||||||
|
30,
|
||||||
62,
|
62,
|
||||||
|
4,
|
||||||
36,
|
36,
|
||||||
|
31,
|
||||||
63,
|
63,
|
||||||
64,
|
64,
|
||||||
|
32,
|
||||||
|
5,
|
||||||
37,
|
37,
|
||||||
|
6,
|
||||||
38,
|
38,
|
||||||
|
7,
|
||||||
39,
|
39,
|
||||||
|
8,
|
||||||
40,
|
40,
|
||||||
|
9,
|
||||||
41,
|
41,
|
||||||
|
10,
|
||||||
42,
|
42,
|
||||||
|
0,
|
||||||
|
68,
|
||||||
69,
|
69,
|
||||||
70,
|
70,
|
||||||
71,
|
71,
|
||||||
|
|||||||
@ -1,75 +1,75 @@
|
|||||||
{ don't edit, this file is generated from mipsreg.dat }
|
{ don't edit, this file is generated from mipsreg.dat }
|
||||||
tregister($00000000),
|
NR_NO,
|
||||||
tregister($01000000),
|
NR_R0,
|
||||||
tregister($01000001),
|
NR_R1,
|
||||||
tregister($01000002),
|
NR_R2,
|
||||||
tregister($01000003),
|
NR_R3,
|
||||||
tregister($01000004),
|
NR_R4,
|
||||||
tregister($01000005),
|
NR_R5,
|
||||||
tregister($01000006),
|
NR_R6,
|
||||||
tregister($01000007),
|
NR_R7,
|
||||||
tregister($01000008),
|
NR_R8,
|
||||||
tregister($01000009),
|
NR_R9,
|
||||||
tregister($0100000a),
|
NR_R10,
|
||||||
tregister($0100000b),
|
NR_R11,
|
||||||
tregister($0100000c),
|
NR_R12,
|
||||||
tregister($0100000d),
|
NR_R13,
|
||||||
tregister($0100000e),
|
NR_R14,
|
||||||
tregister($0100000f),
|
NR_R15,
|
||||||
tregister($01000010),
|
NR_R16,
|
||||||
tregister($01000011),
|
NR_R17,
|
||||||
tregister($01000012),
|
NR_R18,
|
||||||
tregister($01000013),
|
NR_R19,
|
||||||
tregister($01000014),
|
NR_R20,
|
||||||
tregister($01000015),
|
NR_R21,
|
||||||
tregister($01000016),
|
NR_R22,
|
||||||
tregister($01000017),
|
NR_R23,
|
||||||
tregister($01000018),
|
NR_R24,
|
||||||
tregister($01000019),
|
NR_R25,
|
||||||
tregister($0100001a),
|
NR_R26,
|
||||||
tregister($0100001b),
|
NR_R27,
|
||||||
tregister($0100001c),
|
NR_R28,
|
||||||
tregister($0100001d),
|
NR_R29,
|
||||||
tregister($0100001e),
|
NR_R30,
|
||||||
tregister($0100001f),
|
NR_R31,
|
||||||
tregister($02000006),
|
NR_F0,
|
||||||
tregister($02000006),
|
NR_F1,
|
||||||
tregister($02000006),
|
NR_F2,
|
||||||
tregister($02000006),
|
NR_F3,
|
||||||
tregister($02000006),
|
NR_F4,
|
||||||
tregister($02000006),
|
NR_F5,
|
||||||
tregister($02000006),
|
NR_F6,
|
||||||
tregister($02000006),
|
NR_F7,
|
||||||
tregister($02000006),
|
NR_F8,
|
||||||
tregister($02000006),
|
NR_F9,
|
||||||
tregister($02000006),
|
NR_F10,
|
||||||
tregister($02000006),
|
NR_F11,
|
||||||
tregister($02000006),
|
NR_F12,
|
||||||
tregister($02000006),
|
NR_F13,
|
||||||
tregister($02000006),
|
NR_F14,
|
||||||
tregister($02000006),
|
NR_F15,
|
||||||
tregister($02000006),
|
NR_F16,
|
||||||
tregister($02000006),
|
NR_F17,
|
||||||
tregister($02000006),
|
NR_F18,
|
||||||
tregister($02000006),
|
NR_F19,
|
||||||
tregister($02000006),
|
NR_F20,
|
||||||
tregister($02000006),
|
NR_F21,
|
||||||
tregister($02000006),
|
NR_F22,
|
||||||
tregister($02000006),
|
NR_F23,
|
||||||
tregister($02000006),
|
NR_F24,
|
||||||
tregister($02000006),
|
NR_F25,
|
||||||
tregister($02000006),
|
NR_F26,
|
||||||
tregister($02000006),
|
NR_F27,
|
||||||
tregister($02000006),
|
NR_F28,
|
||||||
tregister($02000006),
|
NR_F29,
|
||||||
tregister($02000006),
|
NR_F30,
|
||||||
tregister($02000006),
|
NR_F31,
|
||||||
tregister($05000000),
|
NR_PC,
|
||||||
tregister($05000001),
|
NR_HI,
|
||||||
tregister($05000002),
|
NR_LO,
|
||||||
tregister($05000003),
|
NR_CR,
|
||||||
tregister($05000004),
|
NR_FCR0,
|
||||||
tregister($05000005),
|
NR_FCR25,
|
||||||
tregister($05000006),
|
NR_FCR26,
|
||||||
tregister($05000007),
|
NR_FCR28,
|
||||||
tregister($05000008)
|
NR_FCSR
|
||||||
|
|||||||
@ -10,12 +10,12 @@ RS_R6 = $06;
|
|||||||
RS_R7 = $07;
|
RS_R7 = $07;
|
||||||
RS_R8 = $08;
|
RS_R8 = $08;
|
||||||
RS_R9 = $09;
|
RS_R9 = $09;
|
||||||
RS_R10 = $0a;
|
RS_R10 = $0A;
|
||||||
RS_R11 = $0b;
|
RS_R11 = $0B;
|
||||||
RS_R12 = $0c;
|
RS_R12 = $0C;
|
||||||
RS_R13 = $0d;
|
RS_R13 = $0D;
|
||||||
RS_R14 = $0e;
|
RS_R14 = $0E;
|
||||||
RS_R15 = $0f;
|
RS_R15 = $0F;
|
||||||
RS_R16 = $10;
|
RS_R16 = $10;
|
||||||
RS_R17 = $11;
|
RS_R17 = $11;
|
||||||
RS_R18 = $12;
|
RS_R18 = $12;
|
||||||
@ -26,44 +26,44 @@ RS_R22 = $16;
|
|||||||
RS_R23 = $17;
|
RS_R23 = $17;
|
||||||
RS_R24 = $18;
|
RS_R24 = $18;
|
||||||
RS_R25 = $19;
|
RS_R25 = $19;
|
||||||
RS_R26 = $1a;
|
RS_R26 = $1A;
|
||||||
RS_R27 = $1b;
|
RS_R27 = $1B;
|
||||||
RS_R28 = $1c;
|
RS_R28 = $1C;
|
||||||
RS_R29 = $1d;
|
RS_R29 = $1D;
|
||||||
RS_R30 = $1e;
|
RS_R30 = $1E;
|
||||||
RS_R31 = $1f;
|
RS_R31 = $1F;
|
||||||
RS_F0 = $06;
|
RS_F0 = $00;
|
||||||
RS_F1 = $06;
|
RS_F1 = $01;
|
||||||
RS_F2 = $06;
|
RS_F2 = $02;
|
||||||
RS_F3 = $06;
|
RS_F3 = $03;
|
||||||
RS_F4 = $06;
|
RS_F4 = $04;
|
||||||
RS_F5 = $06;
|
RS_F5 = $05;
|
||||||
RS_F6 = $06;
|
RS_F6 = $06;
|
||||||
RS_F7 = $06;
|
RS_F7 = $07;
|
||||||
RS_F8 = $06;
|
RS_F8 = $08;
|
||||||
RS_F9 = $06;
|
RS_F9 = $09;
|
||||||
RS_F10 = $06;
|
RS_F10 = $0A;
|
||||||
RS_F11 = $06;
|
RS_F11 = $0B;
|
||||||
RS_F12 = $06;
|
RS_F12 = $0C;
|
||||||
RS_F13 = $06;
|
RS_F13 = $0D;
|
||||||
RS_F14 = $06;
|
RS_F14 = $0E;
|
||||||
RS_F15 = $06;
|
RS_F15 = $0F;
|
||||||
RS_F16 = $06;
|
RS_F16 = $10;
|
||||||
RS_F17 = $06;
|
RS_F17 = $11;
|
||||||
RS_F18 = $06;
|
RS_F18 = $12;
|
||||||
RS_F19 = $06;
|
RS_F19 = $13;
|
||||||
RS_F20 = $06;
|
RS_F20 = $14;
|
||||||
RS_F21 = $06;
|
RS_F21 = $15;
|
||||||
RS_F22 = $06;
|
RS_F22 = $16;
|
||||||
RS_F23 = $06;
|
RS_F23 = $17;
|
||||||
RS_F24 = $06;
|
RS_F24 = $18;
|
||||||
RS_F25 = $06;
|
RS_F25 = $19;
|
||||||
RS_F26 = $06;
|
RS_F26 = $1A;
|
||||||
RS_F27 = $06;
|
RS_F27 = $1B;
|
||||||
RS_F28 = $06;
|
RS_F28 = $1C;
|
||||||
RS_F29 = $06;
|
RS_F29 = $1D;
|
||||||
RS_F30 = $06;
|
RS_F30 = $1E;
|
||||||
RS_F31 = $06;
|
RS_F31 = $1F;
|
||||||
RS_PC = $00;
|
RS_PC = $00;
|
||||||
RS_HI = $01;
|
RS_HI = $01;
|
||||||
RS_LO = $02;
|
RS_LO = $02;
|
||||||
|
|||||||
@ -26,6 +26,7 @@ var s : string;
|
|||||||
names,
|
names,
|
||||||
regtypes,
|
regtypes,
|
||||||
supregs,
|
supregs,
|
||||||
|
subregs,
|
||||||
numbers,
|
numbers,
|
||||||
stdnames,
|
stdnames,
|
||||||
gasnames,
|
gasnames,
|
||||||
@ -205,6 +206,8 @@ begin
|
|||||||
readcomma;
|
readcomma;
|
||||||
regtypes[regcount]:=readstr;
|
regtypes[regcount]:=readstr;
|
||||||
readcomma;
|
readcomma;
|
||||||
|
subregs[regcount]:=readstr;
|
||||||
|
readcomma;
|
||||||
supregs[regcount]:=readstr;
|
supregs[regcount]:=readstr;
|
||||||
readcomma;
|
readcomma;
|
||||||
stdnames[regcount]:=readstr;
|
stdnames[regcount]:=readstr;
|
||||||
@ -221,7 +224,7 @@ begin
|
|||||||
writeln('Line: "',s,'"');
|
writeln('Line: "',s,'"');
|
||||||
halt(1);
|
halt(1);
|
||||||
end;
|
end;
|
||||||
numbers[regcount]:=regtypes[regcount]+'0000'+copy(supregs[regcount],2,255);
|
numbers[regcount]:=regtypes[regcount]+copy(subregs[regcount],2,255)+'00'+copy(supregs[regcount],2,255);
|
||||||
if i<length(s) then
|
if i<length(s) then
|
||||||
begin
|
begin
|
||||||
writeln('Extra chars at end of line, at line ',line);
|
writeln('Extra chars at end of line, at line ',line);
|
||||||
@ -275,9 +278,9 @@ begin
|
|||||||
end
|
end
|
||||||
else
|
else
|
||||||
first:=false;
|
first:=false;
|
||||||
writeln(supfile,'RS_',names[i],' = ',supregs[i],';');
|
|
||||||
writeln(confile,'NR_'+names[i],' = ','tregister(',numbers[i],')',';');
|
writeln(confile,'NR_'+names[i],' = ','tregister(',numbers[i],')',';');
|
||||||
write(numfile,'tregister(',numbers[i],')');
|
writeln(supfile,'RS_',names[i],' = ',supregs[i],';');
|
||||||
|
write(numfile,'NR_',names[i]);
|
||||||
write(stdfile,'''',stdnames[i],'''');
|
write(stdfile,'''',stdnames[i],'''');
|
||||||
write(gasfile,'''',gasnames[i],'''');
|
write(gasfile,'''',gasnames[i],'''');
|
||||||
write(stabfile,stabs[i]);
|
write(stabfile,stabs[i]);
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user