* Changed tsuperregisterworklist.get() to always return the last item from the list.

* Reversed sort order of simplifyworklist so nodes with most interferences will get their colors first.
    Since degree of nodes in simplifyworklist before sorting is always
    less than the number of usable registers this should not trigger spilling
    and should lead to a better register allocation in some cases.

  After these changes sysutils.o for i386-win32 is 80 bytes less. :)

git-svn-id: trunk@45857 -
This commit is contained in:
yury 2020-07-25 18:29:59 +00:00
parent 72dc2145e9
commit e6b89c98f5
2 changed files with 15 additions and 5 deletions

View File

@ -343,6 +343,7 @@ interface
procedure clear; procedure clear;
procedure add(s:tsuperregister); procedure add(s:tsuperregister);
function addnodup(s:tsuperregister): boolean; function addnodup(s:tsuperregister): boolean;
{ returns the last element and removes it from the list }
function get:tsuperregister; function get:tsuperregister;
function readidx(i:word):tsuperregister; function readidx(i:word):tsuperregister;
procedure deleteidx(i:word); procedure deleteidx(i:word);
@ -590,9 +591,8 @@ implementation
begin begin
if length=0 then if length=0 then
internalerror(200310142); internalerror(200310142);
get:=buf^[0];
buf^[0]:=buf^[length-1];
dec(length); dec(length);
get:=buf^[length];
end; end;

View File

@ -929,7 +929,17 @@ unit rgobj;
{Sorts the simplifyworklist by the number of interferences the {Sorts the simplifyworklist by the number of interferences the
registers in it cause. This allows simplify to execute in registers in it cause. This allows simplify to execute in
constant time.} constant time.
Sort the list in the descending order, since items of simplifyworklist
are retrieved from end to start and then items are added to selectstack.
The selectstack list is also processed from end to start.
Such way nodes with most interferences will get their colors first.
Since degree of nodes in simplifyworklist before sorting is always
less than the number of usable registers this should not trigger spilling
and should lead to a better register allocation in some cases.
}
var p,h,i,leni,lent:longword; var p,h,i,leni,lent:longword;
t:Tsuperregister; t:Tsuperregister;
@ -958,7 +968,7 @@ unit rgobj;
leni:=0; leni:=0;
if adji<>nil then if adji<>nil then
leni:=adji^.length; leni:=adji^.length;
if leni<=lent then if leni>=lent then
break; break;
buf^[i]:=buf^[i-p]; buf^[i]:=buf^[i-p];
dec(i,p) dec(i,p)
@ -1018,7 +1028,7 @@ unit rgobj;
var n:cardinal; var n:cardinal;
begin begin
{If we have 7 cpu registers, and the degree of a node is 7, we cannot {If we have 7 cpu registers, and the degree of a node >= 7, we cannot
assign it to any of the registers, thus it is significant.} assign it to any of the registers, thus it is significant.}
for n:=first_imaginary to maxreg-1 do for n:=first_imaginary to maxreg-1 do
with reginfo[n] do with reginfo[n] do