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* arm thumb: generate proper code for rol

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git-svn-id: trunk@24414 -
This commit is contained in:
florian 2013-05-03 20:53:58 +00:00
parent cec28ef512
commit f3b7f6197b
1 changed files with 2 additions and 1 deletions
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3
compiler/arm/cgcpu.pas
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@ -3775,7 +3775,8 @@ unit cgcpu;
internalerror(2008072801);
{ simulate ROL by ror'ing 32-value }
tmpreg:=getintregister(list,OS_32);
list.concat(setoppostfix(taicpu.op_reg_reg_const(A_RSB,tmpreg,src,32),PF_S));
a_load_const_reg(list,OS_32,32,tmpreg);
list.concat(taicpu.op_reg_reg(A_SUB,tmpreg,src));
list.concat(taicpu.op_reg_reg(A_ROR,dst,src));
end;
else