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* fix typo
* properly pass zba, zbb, zbs to march
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parent
4664e510e6
commit
fecd25bac1
@ -231,14 +231,14 @@ unit agrvgas;
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function TRVGNUAssembler.MakeCmdLine: TCmdStr;
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const
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arch_str: array[boolean,tcputype] of string[10] = (
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arch_str: array[boolean,tcputype] of string[18] = (
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{$ifdef RISCV32}
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('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32imafdc','rv32imafd','rv32ec','rv32gc'),
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('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32imafdc','rv32imafd','rv32ecfd','rv32gc')
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{$endif RISCV32}
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{$ifdef RISCV64}
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('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc','rv64gcb'),
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('','rv64imafdc','rv64imafd','rv64imfd','rv64ifd','rv64imafdc','rv64imafd','rv64gc','rv64gcb')
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('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc','rv64gc_zba_zbb_zbs'),
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('','rv64imafdc','rv64imafd','rv64imfd','rv64ifd','rv64imafdc','rv64imafd','rv64gc','rv64gc_zba_zbb_zbs')
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{$endif RISCV64}
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);
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begin
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@ -90,7 +90,7 @@ implementation
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if CPURV_HAS_ZICOND in cpu_capabilities[current_settings.cputype] then
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attr_arch:=attr_arch+'_zicond1p0';
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if CPURV_HAS_CSR_INSTRUCTIONS in cpu_capabilities[current_settings.cputype] then
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attr_arch:=attr_arch+'_zicrs2p0';
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attr_arch:=attr_arch+'_zicsr2p0';
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if CPURV_HAS_FETCH_FENCE in cpu_capabilities[current_settings.cputype] then
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attr_arch:=attr_arch+'_zifencei2p0';
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if CPURV_HAS_ZMMUL in cpu_capabilities[current_settings.cputype] then
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